Programmable logic devices support hot-socketing

Altera has implemented the support for hot socketing and power sequence protection in its advanced PLD families - Stratix, Stratix GX, Cyclone, MAX 7000AE and MAX 3000A devices.

The fundamental idea behind hot socketing in PLDs is to turn off the output buffer during the power-up (either VCCINT or any of the VCCIO supplies) or power-down event. The hot-socket circuit will generate an internal HOTSCKT signal when either VCCIO or VCCINT is below the threshold voltage. The HOTSCKT signal will cut off the output buffer to make sure no DC current (except for leaking current through the weak pull-up resistor) is going through the pin.

When VCC ramps up very slowly, it is still relatively low even after the power-on-reset (POR) signal is released and the configuration of the FPGA device is finished. If the hot-socketing circuit were implemented on the device's CONF_DONE, nSTATUS, and nCEO pins, they would fail to respond because the output buffer could not flip from the state set by the hot-socketing circuit at this low VCC voltage. To overcome this issue, the hot-socketing feature is removed on these pins to make sure that the CONF_DONE, nSTATUS, and nCEO pins can operate during configuration. This is the expected behavior as these pins are supposed to drive out during power-up and power-down sequences.

Figure 1 shows the hot-socketing implementation in Altera PLDs. The POR circuit monitors VCCINT voltage level and keeps I/O pins tristated until the device is in the user mode. The weak pull-up resistor from the I/O pin to VCCIO prevents the I/O pins from floating. The voltage tolerance control circuit allows the I/O pins to be driven before VCCIO and/or VCCINT are powered, and it prevents the I/O pins from driving out when the device is not in the user mode. The hot socket circuit prevents I/O pins from internally powering VCCIO and VCCINT when driven by external signals before the device is powered. On the transistor level of the FPGA device I/O buffer (Fig. 2), the CMOS output drivers in the I/O pins intrinsically provide electro-static discharge (ESD) protection in the Stratix, Stratix GX and Cyclone FPGA families from Altera. There are two cases to be considered for ESD voltage strikes: positive voltage zap and negative voltage zap.

A positive ESD voltage zap occurs when a positive voltage is present on an I/O pin due to an ESD charge event. This can cause the N+ (Drain)/P-Substrate junction of the N-channel drain to break down, and the N+ (Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turns on to discharge ESD current from I/O pins to GND. When the I/O pin receives a negative ESD zap at the pin that is less than -0.7 V (0.7 V is the voltage drop across a diode), the intrinsic P-Substrate/N+ drain diode is forward biased. Hence, the discharge ESD current path is established from GND to the I/O pin.

The latest FPGA devices are embedded with high-speed serial transceivers to meet the demands from communications, networking and storage equipments that are adopting the serial data transfer technology in their backplane architectures. It is critical that the embedded transceivers also support hot-socketing so that they are not intrusive to the data connections in the backplane during hot-swapping. Altera's Stratix GX family has on-chip high-speed serial transceivers that are designed to support hot-socketing.

In multi-voltage systems for which hot swapping is not required, hot-socketing and power-sequence-protection capability of the PLDs still can be critical. In these systems, regulators are used to provide different voltage levels and can cause the power-up sequence to be difficult to predict; devices that require a predetermined power-up sequence may no longer function properly.

Justin Bennett is Senior Component Application Engineer and Hsiao-chuan (John) Hu is Senior Product Marketing Engineer at Altera Corp. (San Jose, Calif.)