Crafting wafer-scale strained silicon

Before advances in epitaxy, lower strain levels induced by CMOS processing and chip packaging were known to affect device performance, but these were avoided because of inconsistent strain control and a lack of understanding of the strain's origin. But through epitaxy, uniform significant strain levels can be introduced into the substrate material itself because of the atomic nature of the induced strain.

The main method for making a wafer-scale strained silicon layer that is process independent and uniform is the creation of a virtual Si1-xGex substrate. Because the silicon germanium lattice is larger than the silicon lattice, when a thin silicon layer is deposited on this SiGe substrate the atoms reproduce the SiGe crystal lattice spacing, forcing the silicon atoms to be farther apart than they are in native silicon. Thus, the silicon layer experiences stress in the wafer plane, creating a tensile strain in that plane. This strain affects the band structure of silicon, increasing the in-plane mobility of electrons and holes, thereby increasing drive currents in MOSFET structures.

The greatest difficulty in achieving high-quality strained silicon is creating the native lattice constant of SiGe when SiGe is deposited on a substrate. As for strained silicon, SiGe will initially mimic the silicon lattice, putting strain in the SiGe. If the SiGe remains strained, any silicon deposited on the SiGe will have the native silicon lattice constant, and therefore the silicon will not be strained. Thus, the SiGe must be relaxed to its native SiGe lattice. SiGe deposition must proceed through a strain-relaxation process. At film-deposition temperatures, semiconductors are ductile, which means they relax through dislocation formation and motion-no other process relaxes the strain significantly at elevated temperatures. If SiGe is directly deposited on silicon and grown with enough thickness, dislocations are introduced to relieve the stress, and the ends of the dislocations can travel up to the top surface. High densities of dislocations (106 cm2 and greater) affect performance and reliability of minority and majority carrier devices.

Dislocations must be introduced to relax the SiGe lattice, yet few must reach the surface. This paradox has been solved by using an epitaxial graded germanium composition SiGe region in which the dislocation formation and motion can be controlled independently, leading to relaxed SiGe layers with low threading-dislocation densities. This fundamental aspect of graded layers is unique to this method and is required for achieving extremely low threading-dislocation densities in strained silicon. In addition, since the dislocation density at the surface decreases and growth rate increases as the temperature of the process is increased, nature dictates that the highest-quality wafers will be the lowest-cost ones. Current infrastructure already prevalent in the industry can produce these wafers, and recent processes have been demonstrated that can produce multiple wafers per hour on a single-wafer industry tool with surface dislocation densities less than 1 x 105 cm2 and with industry-standard surface smoothness. This rate of production in high volumes will produce strained silicon wafers at low cost.

For the above reasons, we show in the figure the starting source of strained silicon is a relaxed Si1-xGex layer on silicon. This wafer can be processed into what is referred to as bulk strained silicon, that is, a strained silicon layer on the virtual SiGe substrate. This wafer can be processed into CMOS, increasing the frequency of operation or lowering the active power consumption of CMOS circuits. This same bulk strained silicon can be surface-bonded to an SiO2/Si wafer; by using selective methods of layer removal the original SiGe and silicon substrate can be removed, creating strained silicon on insulator (SSOI).

Alternatively, the virtual substrate can be bonded to SiO2/Si, creating SiGe on insulator (SGOI), which subsequently can have strained silicon deposited on it through another epitaxy process. In all cases, the perfection of the relaxed SiGe buffer determines the perfection of the final device layers.

All platforms (bulk strained silicon, SGOI, SSOI) can also benefit from even more enhanced-mobility channels created by strained silicon, strained SiGe and strained germanium layers (also see http://sauvignon.mit.edu/ssoi/Fitzgerald-ECS-2003.pdf). Additional layers can be deposited on virtual substrates as strained silicon is deposited, and layer transfer to on-insulator (OI) platforms will transfer those channel layers as well.

The good and the bad

The core benefit of all of these platforms is strained silicon. The strain increases the current in the transistor, the primary parameter. For this reason, significant strain in an engineered substrate is a dominant performance factor. Because the core aspect of the transistor is affected, the improved transport properties of the MOSFET can be captured directly in existing EDA tools. For germanium concentrations in the virtual buffer of approximately 20 percent, n-channel MOSFETs have an 80 percent increase in mobility, resulting in a 20 percent to 30 percent increase in current drive for a short-channel (90-nanometer to 25-nm) n-channel MOSFET. P-MOSFETs are enhanced to a lesser extent at this level of strain, that is, at this composition of germanium in the virtual substrate. Current drive enhancement is independent of platform (bulk strained silicon, SGOI, SSOI) and independent of technology node down to at least the 45-nm level. This point is very important, since strained silicon benefits all MOS generations, and therefore has the potential of being very scalable.

The advantages and disadvantages of the various strained platforms that include on-insulator technology are additive. In terms of advantages, on-insulator technology affects the parasitics of the MOSFET much the way SOI does. A main benefit, for example, is a reduced capacitance of the source-drain region, and such benefits are not affected by combining strained silicon and OI. In terms of disadvantages, the same problems are introduced as occur in SOI, such as floating-body effects and the need for specialized design tools for partially depleted OI, and the need for raised source-drain and metal gates for fully depleted OI.

There are two known exceptions to the additive rule, one positive in synergy, one negative. In platforms in which the SiGe is in contact with SiO2 on the back interface (for example, SGOI), fully depleted structures have a degradation in subthreshold current due to the intrinsic high charge at the back interface. In SSOI, the absence of SiGe holds two positive synergistic effects. First, Ge interdiffusion during processing is not a concern. Second, the germanium-induced subthreshold current degradation is absent.

Markets and adoption

There are certain technological features that set adoption boundaries.

For bulk strained silicon wafers, a long history of research and development has led to a commercial process that can produce high-quality bulk strained silicon at low cost. However, outside of the technology-specific characteristics that have been satisfied (low surface dislocation densities, high surface planarity), there are other inherent wafer qualities that require high volumes to drive perfection and cost reduction, as with any wafer product. Increasing the supply of bulk strained layers is the key to all strain-based technologies, as implied in the figure.

The increased supply will be generated by increased market pull. The early adopters of new silicon CMOS technologies (scaling) are companies that sell into markets in which the integrated circuits typically have very large dice and house a large number of transistors. Due to the large die size, great perfection (such as low particle counts) is required for these applications when running at production levels. Increasing R&D demand for wafers is one phenomenon that is helping to overcome the volume barrier. Standardization will aid in adoption as R&D resources can be focused on a bulk strained silicon standard. Ultimately, since the current enhancement is fairly independent of technology node from 90 nm to 25 nm, and the current enhancement is even larger for earlier nodes, many products on bulk silicon can benefit over time from bulk strained silicon. Early adoption of strained silicon can move beyond microprocessors, digital signal processors and other large-die-size products once volume is driven initially by these markets.

SSOI platforms will also become available as bulk strained silicon volume increases, since commercial SOI interest has created infrastructure that can add on-insulator technology to semiconductor materials. In general, methods of layer transfer to form SSOI and SGOI require greater materials perfection; once a high-volume, high-quality, low-cost supply is available, strained SOI platforms will be possible. Most early adopters anticipate the eventual need for such platforms.

Since the technology of strained silicon and on-insulator have additive advantages and disadvantages, the market adoption of on-insulator platforms will not be affected by strained silicon. The boundary between bulk and on-insulator platform markets is a consequence of the advantages and disadvantages of on-insulator technology. Strained technology will appear on bulk and on OI, but will likely not affect this boundary appreciably.

Finally, it is interesting to note that materials advances in channel engineering through strained silicon, SiGe and germanium are occurring in research much faster than the rate at which technologies can be absorbed by the early adopters of scaled-silicon technology. This absorption issue suggests that some of the more advanced strained channels may first find their way into low-volume, high-performance small-die circuits. It is possible that as the volume of materials and products increases in these smaller markets, eventually some of these advanced channels will appear in products currently produced by the industry's early adopters of scaled silicon technology.

Eugene A. Fitzgerald is Merton C. Flemings SMA Professor of Materials Engineering at MIT. Fitzgerald is co-founder and chairman of AmberWave Systems, Inc. (Salem, NH).

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