Engineered substrates boost performance

International forums like the International Electron Devices Meeting (IEDM) and the Symposium on VLSI Technology provide the proof of concept and underline the advantages of the solutions supported by the new composite substrates. Strained silicon, germanium on insulator on Si substrate (GeOI), 3-D wafer-level IC layer transfer and novel SOI crystal orientations for FinFET optimization are just a few examples of the ongoing developments in the R&D community. Substrate engineering has acquired a critical importance for IC integration, adding new materials to the making of advanced "silicon substrates."

IC makers, equipment producers, material suppliers, wafer manufacturers, startups and academia have caught on to the new technology trends, generating massive intellectual property and exciting results as well, but leaving the most important question unanswered: "Where are the industrial solutions to satisfy the wafer needs of the IC industry along the Moore's Law technology path?" The reality is the acceleration of the chip industry and the issues to be addressed by the emerging materials have caused the industry at the bottom of the IC food chain to be caught by surprise.

The reason for intentionally inducing strain in silicon is the biaxial distortion of the crystal lattice. The distortion changes the electronic band structure in such a way that it improves electron and hole mobility by up to 50 to 80 percent, depending on the degree of strain. It improves IC performance by 20 to 30 percent. High-k metal oxides, another emerging material in MOSFET architecture, make possible a further reduction of the effective SiO2 gate oxide thickness below the SiO2 leakage limited thickness. The drawbacks are integration problems and the electrical quality of the Si/dielectric interface that may lead to decreased mobility.

One way to circumvent these hurdles is GeOI, since metal oxides are an excellent match for germanium and this new material set should allow GeOI to achieve very high-mobility, very high-performance MOS devices.

However, there's concern that today's metal oxides are far from being mature enough to replace silicon dioxide or oxynitrides as gate dielectrics in high-volume manufacturing. The same statement holds true for germanium thin films on insulator as a replacement for SOI substrates.

Fabricating strained SOI requires expertise in two areas: epitaxy of strained silicon and SiGe, and formation of ultrathin SOI. In order to best satisfy these needs, Soitec has partnered with ASM International (ASMI; Netherlands) to put in place the first 200- and 300-mm industrial infrastructure to accelerate the early manufacturing of the most advanced-engineered substrates:

- Strained silicon on a SiGe ultrathin film on insulator (SGOI) for partially depleted device architectures, and

- Strained silicon directly on insulator (sSOI) for fully depleted device architectures.

The sSOI method is the preferred substrate solution for the 65-nm and 45-nm technology nodes, respectively. The ASMI-Soitec alliance combines the industrial expertise in leading-edge transfer technology-Smart Cut, epitaxy and thermal processing with a strong commitment to 300 mm.

The figure (page 52) shows an example of the SGOI wafers currently sampling. The SiGe is more than 95 percent relaxed, the Si is strained by 1.5 gigaPascals stress induced by the lattice mismatch, with a minimum-maximum total strain variation of 6 percent, and the strained Si-to-SiGe interface is very sharp. TOF-Sims characterization shows that the Ge concentration is homogeneous across the thickness of the SiGe film with no Ge pileup or diffusion into the strained Si top layer. This highlights the power of the Smart Cut as an industrial tool to tailor engineered substrates to the stringent requirements of state-of-the-art IC processing.

Metrology role

Continuous in-house improvement programs are no longer sufficient. The equipment and material makers must join forces very early in the development of advanced engineered substrates in order to achieve a timely solution. Metrology plays a key role in the development of composite wafers. In some cases metrology limitations can become a gating factor for further improvement of advanced substrates. Thus, the introduction of new materials requires not only industrial partnerships between equipment and material suppliers, but also a more proactive participation by the metrology industry. An early involvement of metrology in substrate engineering has become a must.

Carlos Mazure is chief technical officer at Soitec (Bernin, France).

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