Non-Classical CMOS: the "Ultimate" MOSFET Device

Figure 1. Schematic cross-section of planar bulk MOSFET (from M. Bohr, 'MOS Transistor Scaling Challenges,' reproduced by permission of The Electrochemical Society, Inc.)

A key enabler of Moore's Law has been continuous scaling (reduction) in all the physical dimensions of the MOSFET and its contacts (see Figure 1 for a schematic cross-section (1)), and in the DC power supply voltage applied to the MOSFET. However, with scaling, a number of difficulties arise in meeting the transistor requirements. One such difficulty is a sharp increase in the gate leakage current as the thickness of the silicon oxynitride gate dielectric is scaled to the current state of the art of about 1.5 nm and below. A solution under active investigation to reduce the gate leakage current is the use of alternate, high-k materials for the gate dielectric (2). Other difficulties that become increasingly severe with transistor scaling include polysilicon depletion in the gate electrode and limits in doping the channel and the source and drain. Material and processing solutions to these problems such as alternate metal gate electrode materials, new doping and annealing approaches for the source and drain, elevated source and drain, and techniques such as advanced "HALO" implant for engineering the channel are being pursued by the industry.

As MOSFET scaling continues, in 2007 the transistor gate length (Lg) is expected to be around 25 nm, compared to 45 nm for today's leading-edge transistors. By 2007, and especially beyond 2007, it is expected that scaling will result in increasing difficulties for planar bulk MOSFETs in meeting all of the transistor requirements, even with the utilization of high-k gate dielectric, metal electrodes, novel annealing schemes, and the other material and processing type potential solutions mentioned above (3). Key challenges are expected to include difficulty in controlling short-channel effects (undesirable shifts in transistor electrical characteristics, including increased leakage current and reduced threshold voltage, as Lg becomes small), negative impact of the high channel doping required for very small devices, difficulty in obtaining adequate drive current (Ion) in the on state for transistors with very small Lg, as well as other issues. Non-classical MOSFETs, including devices with enhanced mobility channels (i.e., strained silicon channels) as well as ultra-thin body silicon-on-insulator (SOI) single-gate MOSFETs and various types of double-gate MOSFET, are being investigated and may be utilized as a solution (4).

In transistors with strained silicon channels, the strained silicon has enhanced mobility and hence the Ion is larger than for transistors with unstrained channels. Two layers of mixed silicon-germanium (Si1-yGey, where the bottom layer has graded germanium concentration, y, and the top layer has a fixed germanium concentration) are epitaxially grown on a silicon (Si) substrate. A thin layer of Si is then epitaxially grown on the silicon-germanium layer, and this top layer of Si forms the channel of the MOSFET, where the current flows when the device is turned on. Due to the difference in the lattice spacing of the Si and the upper silicon-germanium layer, the top Si layer is subjected to tensile strain, and as a result of this strain, the top Si layer exhibits enhanced mobility. The germanium concentration of the upper silicon-germanium layer is fixed at a value calculated to produce optimal strain in the top Si layer. Strained silicon channel MOSFETs are likely to be implemented into production within the next several years.

Ultra-thin body SOI has a very thin layer of single-crystal silicon, the ultra-thin silicon body, on top of a silicon dioxide insulating layer (the buried oxide, or "BOX"), which itself is on top of the silicon substrate. (SOI wafers are available from several global suppliers.) The ultra-thin body forms the channel of the MOSFET. The advantages of ultra-thin body SOI for highly scaled MOSFETs include reduced junction capacitance, improved electrical isolation, the possibility of optimal operation with relatively light channel doping, and certain advantageous circuit characteristics. The ultra-thin body SOI may be either a single-gate (similar to the planar structure in Figure 1) or a double-gate MOSFET.

One type of double-gate MOSFET is similar to the ultra-thin body SOI single-gate transistor, with the addition, in the BOX, of a bottom gate electrode fully self-aligned to the top gate electrode. The double-gate MOSFET has superior scalability (i.e., superior control of short-channel effects) for very small MOSFETs, due to the electrical shielding action of the bottom gate for electric fields originating from charges in the source and drain. Also, since current can flow along both the top and bottom edges of the silicon body, rather than just along the top edge as in the ultra-thin body SOI single gate MOSFET, the Ion can almost double that of the single-gate device. The superior scalability of double gate is highly advantageous for MOSFETs as Lg is scaled below 25 nm. However, there are major issues with the complicated process flow required (hence high cost) and difficult manufacturability issues.

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Figure 2. Schematic drawings of FinFET.

Double-gate MOSFETs can be made in other configurations as well. The leading candidate currently is the FinFET(1,5), since it can be fabricated with a process flow that utilizes techniques and tools relatively similar to those currently utilized for fabricating planar bulk MOSFETs. FinFETs are illustrated schematically in Figure 2. The FinFET is formed by defining and etching thin fins (shown in yellow in the figure) in the silicon body of an SOI wafer. Polysilicon gate electrodes are defined surrounding the fin, as shown in the dark color in the figure. In this case, the double gates are on the left and right sides of the fin. When the MOSFET is turned on, the current flow is from source to drain, along both the left and right vertical edges of the fin.

For the "ultimate" scaled MOSFET beyond 2015 or so, Lg is projected to be 10 nm and below. To meet the requirements for such highly scaled transistors, it is likely that double-gate MOSFETs with enhanced mobility channel and a number of the process and material solutions noted earlier, such as high-k gate dielectric, will be utilized.

References

(1) M. Bohr, "MOS Transistor Scaling Challenges," Proceedings of the International Symposium ULSI Process Integration II, March 2001, in ECS Proceedings Volume 2001-2, 463-473 (2001).

(2) H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C.D. Young, P.M. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner and R.W. Murto, "High-K Gate Stacks Into Planar, Scaled CMOS Integrated Circuits," (presented at the Conference on Nano and Giga Challenges in Microelectronics (2002), Moscow, September 10-13, 2002, to be published in Microelectronic Engineering (2003).

(3) P.M. Zeitzoff, J.A. Hutchby and H.R. Huff, "MOSFET and Front-End Process Integration: Scaling Trends, Challenges, and Potential Solutions Through The End of The Roadmap," International Journal of High-Speed Electronics and Systems, 12, 267-293 (2002).

(4) H. R. Huff and P.M. Zeitzoff, "The "Ultimate" CMOS Device: A 2003 Perspective (Implications For Front-End Characterization And Metrology," Presented at the 2003 International Conference on Characterization and Metrology for ULSI Technology (March 24-28, 2003), to be published in the Conference Proceedings (AIP Press).

(5) N. Lindert, L. Chang, Y.-K. Choi, E.H. Anderson, W.-C. Lee, T.-J. King, J. Boker and C. Hu, "Sub-60-nm Quasi-Planar FinFETs Fabricated Using a Simplified Process," IEEE Electron Dev. Lett., 22, 487-489 (2001).

Peter M. Zeitzoff and Howard R. Huff are with International SEMATECH in Austin, TX