New devices needed for speed crunch

The dot-com revolution may have slowed, but a variety of factors is making a profound impact on design requirements in the Internet infrastructure. The deployment of faster broadband pipes to end users and the increasing reliance by Web sites on multimedia content such as graphics, sound, music and video continue to drive up Internet traffic rates. At the same time, businesses are increasingly using the Internet for mission-critical functions from sales to organizational communications. Driven by new applications in e-business, enterprise resource planning and customer relationship management, the quantity of data stored by organizations is doubling every year.

One effect of this evolution is the emergence of two distinctly different types of traffic being transmitted over the Internet-sequential and random. Much of the data being transmitted across the Net remains sequential in nature. But the emergence of faster pipes to end users and the widespread deployment of multimedia content are driving up the use of time-sensitive data. Today an increasing portion of Internet traffic, usually in the form of voice and video, must arrive on time to be functional. Moreover, this new type of traffic is typically characterized by extremely large files, placing new bandwidth demands on the Internet infrastructure.

The key to maximizing data throughput in this new environment lies in the construction of sophisticated data-buffering, filtering and policing mechanisms. In some cases, the system must take multiple data streams and concentrate them into a single data stream. In other instances, the system must take a single data stream and distribute it efficiently across multiple data streams. The question for today's communications system designers is how best to manage this new set of data-aggregation, data-segregation and data-prioritization issues as they attempt to build the data flow management mechanisms needed to optimize throughput.

Falling off-the-shelf

Until now, router and switch designers have largely resorted to one of two options: off-the-shelf or custom devices.

In some cases they have turned to multichip solutions that combine logic and off-the-shelf specialty memories such as FIFOs or multiport SRAMs. Designers seeking to multiplex multiple data streams together, for example, might craft a solution with a combination of standard logic and FIFOs.

Memory subsystems built from off-the-shelf specialty memories and digital logic are inexpensive and relatively easy to implement. But off-the-shelf FIFOs and multiport SRAMs, for instance, are generally not available on a cost-effective basis in densities above 9 Mbits. Accordingly, designers often find that these off-the-shelf solutions cannot offer the density or granular control that today's high-speed communications systems designs require.

Alternatively, designers try to solve this problem with a more customized approach using application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Such so-called homegrown solutions offer a very high degree of flexibility.

By building a solution inside an ASIC or FPGA, for example, designers can integrate random-access capability into a FIFO block. For designers trying to address the management of sophisticated subscription rates where a system might have to support dedicated bandwidth requirements or sort through sequential data and prioritize it, those advantages can be highly attractive.

In addition, a single-chip ASIC or FPGA solution lowers system parts count and occupies minimal board real estate. Moreover, since ASIC and FPGA vendors now offer standardized intellectual-property blocks, these solutions are increasingly simple to implement.

Conflicts ahead

But designers opting for this approach must overcome some formidable obstacles. First and foremost is cost. ASICs require a large nonrecurring expense investment up front, and FPGA part costs-especially for high-density, high-speed devices-are high relative to the cost of off-the-shelf memory and logic. Further, solutions designed to prioritize and buffer multimedia traffic often require data pipes that are both fast and wide. That conflicts directly with the I/O limitations associated with programmable logic.

The other problem inherent in the use of either homegrown or multichip, off-the-shelf solutions is their cost in terms of design time and effort. Designers using an ASIC/FPGA solution or integrating off-the-shelf memory and logic ICs spend considerable time designing, simulating and testing the architecture. Before they implement a system, they must guarantee that all corner cases will be met in a production environment. Instead of devoting all their time to router and switch design, they often end up expending significant effort designing logic and memory subsystems.

What is needed to solve these network data path and control applications is a new type of semiconductor device. Ideally, these new devices would combine critical logic functions from a variety of specialty memories such as memory controllers, multilevel queue controllers and multiplexing/demultiplexing controllers with a variety of sequential blocks and clock-critical circuits.

These devices would provide designers with the first fresh approach to both sequential and random data acquisition and manipulation using a single, highly integrated device to address the segregation and prioritization issues associated with time-sensitive Internet traffic.

By leveraging many of the distinct characteristics of off-the-shelf FIFOs, multiport SRAMs, specialty DRAMs and highly optimized flow-control logic in multiple configurations, these new architectures would help address the evolving needs of today's communications systems designers.

Instead of implementing network bridging and multiplexing and demultiplexing functions using traditional approaches based on ASICs or FPGAs, designers would be able to use these new off-the-shelf devices to manage data flow control issues in their communications equipment designs.

Cost, time drops

Included in this new part family, for example, might be a device that features four independent ports on one side, each with its own data memory block, and a single bus on the other side. By supporting bandwidths in the multigigabit/second range, these devices could serve as ideal solutions for router and switch applications that require data stream convergence or parallel buffering of multiple data paths. That, in turn, would allow designers to offload their ASICs and FPGAs to more critical processing tasks.

The cost benefits of this new class of devices would be dramatic. Available in multiple configurations off the shelf, they would offer a significantly lower cost structure than any competing custom solution.

Perhaps just as important, these new devices would relieve the router and switch designer of the time-consuming task of building a highly specialized logic and memory subsystem. Designers would no longer have to worry about designing, simulating and testing multichip solutions or ASICs and FPGAs.

With an off-the-shelf solution, they could simply integrate the part into their system design and use the supplier's models to resolve all simulation, testing and timing issues. Ideally, that would free up more time to focus on the truly innovative aspects of their router or switch architecture. Ultimately, these advantages promise to dramatically shorten product development schedules and improve time-to-market.

Clearly the Internet is undergoing a major transformation. The types of data transmitted across it are rapidly changing. A new reliance on time-sensitive data, larger packet sizes and faster transmission rates is bringing to the forefront a new set of data flow management issues for router and switch designers. The most efficient way to resolve these design challenges will be to use a new class of semiconductor devices that captures many of the performance advantages of custom ASIC and FPGA solutions in a cost-effective, off-the-shelf format.

Michael Olsen is director of strategic marketing at Integrated Device Technology Inc. (Santa Clara, Calif.).

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