Ensuring the thermal integrity of your IC package/PC board design

Maintaining the integrity of your circuit design over increasing ambient temperature by keeping IC junction temperature comfortably away from the absolute maximum level is an important design consideration when it comes to the reliability of your overall design. This is especially true when you are pushing towards the maximum power dissipation levels (Pd max) of the particular chip central to your circuit design.

The first step in your thermal integrity analysis is to better understand the basics of IC package thermal metrics (Reference 1)

By far the most common measure of package thermal performance is Theta JA (sometimes denoted formally by θ_JA or θ_ja, but pronounced "Theta-J-A", and often just written as Theta JA, with no Greek character used), the thermal resistance measured (or modeled) from junction to ambient (Figure 1).

Figure 1: Theta-JA analogy to electrical network
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Theta JA values are also the most subject to interpretation (Figure 2).

Figure 2: Theta-JA explained.
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Factors that can greatly influence the measurement and calculation of Theta JA are:

• Board mounted: yes/no?
• Traces: size, composition, thickness, and geometry
• Orientation: horizontal or vertical?
• Ambient: volume
• Proximity: any other surfaces near the device being measured?

Included with the junction-to-ambient data is junction-to-case (Theta JC) thermal resistance data (Figure 3). Actual Theta JC data was generated for the packages tested using the JEDEC printed circuit board (PCB).

Figure 3: Explanation of Theta-JC
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Wow, who has the time or patience to go through all of this analysis and testing " except JEDEC, of course! In this article, you will learn how to safely bypass these steps when testing the thermal integrity of your design.

You can access thermal data for the particular package you are using by going to thermaldata. Here you will find the derating curve, Tja, with different moving-air linear feet per minutes (LFM) and other modeled data important to your design (Reference 2).

All this information will help you to not exceed maximum junction temperature of the device. Of special importance is the adherence to manufacturer and JEDEC-recommended package layout guidelines, for example, for those using a QFN package (Reference 3). Following these types of design recommendations can help you to implement the best thermal design possible.

Now that you have the fully modeled thermal overview and verified your board layout and thermal design, let's find out how good your thermal design actually is without using thermal modeling software or thermocouples to measure the actual case temperature. Theta JA rating in a data sheet is usually based upon an industry standard like JEDEC #JESD51, which uses a standardized layout and test board. Therefore, your thermal design probably will be different and actually have a different Theta JA than the standard because of your particular PC board design needs.

If you want to know how close to an optimum thermal design your design is, do the following in-system test for your particular PC board design. (Try setting voltages to their maximum possible values to test worst-case conditions.)

For best results, use an oven (not a thermal induction system) and measure Ta only near the board, since ovens have hot spots. If possible, use a thermal-insulating mat on the underside of the board to prevent room temperature air from tainting the measurement.

First, find out the actual thermal resistance of your IC in its actual design environment (PC board). Then compare it to the "ideal" JEDEC numbers. You will need an IC with a thermal error flag (TEF) or similar function that indicates an over-temperature condition at the junction of the IC. For example, we used TI's TLC5940 LED driver-solution chip. Typically the maximum Tj for most ICs (check your datasheet for actual number) is around 150° C. In the case of the TLC5940 device, the TEF will trip at Tj between 150° and 170° C.

In our test here, we care only what the Tj of the particular chip on our test board is. We use this as a reference to substitute in an equation that gives us the thermal resistance Theta JA of the particular PC board being tested. This should be fairly indicative of our thermal design quality.

Test several PC boards for a good sampling of the solder integrity of areas such as the PowerPad™ for correct use of this unique package heat-sink technology, if the chip has this type of heat sink. To find the device's maximum Tj allowed by the TEF, put the PC board in a temperature chamber with the device seeing no load and running only at quiescent conditions. Slowly increase the chamber temperature until the TEF is triggered. The temperature point where the chamber is at when this happens is the Tj since Ta = Tj.

In this case, it is when power dissipation (Pd) is essentially at very low quiescent levels and can be considered zero. Record this temperature as Tj. It will be used in our equation for Theta JA coming up (Reference 4).

Second, find your circuit's maximum Pd. Raise the chamber temperature to around 10 or 15 degrees above the IC maximum ambient temperature as specified in the data sheet (record this temperature value as Ta). This will let the TEF trip quicker through self-heating.

Now we apply a full load to the IC by increasing Pd slowly until the TEF is tripped. In the TLC5940 we can vary the external resistor R(IREF), which sets the device's Io sink current. If the over-temperature circuit has hysteresis, then the circuit will temperature cycle slowly, requiring us to slowly reduce Pd until the cycling stops. At this point the chamber temperature should be recorded as Pd max.

Finally, to get your board's Theta JA, insert the measured values of Tj, Ta and Pd maximums into the following equation:

Theta JA = (Tj-Ta)/Pd max

If you have a good thermal design, this value should be close to the Theta JA in the IC data sheet.

Fortunately, this test does not rely on the direct measurement of the temperature of the case (Tc) or junction (Tj), which is very difficult to accurately measure in situ.

Some tips:

• Be sure to have a few minutes to soak the PC board in the chamber at temperature
• Take into account the IC power dissipation at Iq by adding Vsupply × Iq to the ideal Pd. This may or may not be a negligible factor.

Table 1: Dissipation Ratings
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• Increase the PC board copper thickness that is dissipating the IC heat through the PowerPad or other thermal heat sink device used.
• Decrease the maximum ambient temperature that the IC sees by using air flow, if possible.
• Lower the device's Pd. In our test, this can be done in a number of ways (see Figure 4):
1. Lower the V_LED)
2. Add a series resistor to the LED current path. This will not change the total power dissipated in the design, but it will remove some of the Pd from the IC package to the external series resistor.

Figure 4: TLC5940 cascaded application example reference for techniques to improve thermal design.
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Summary
Good circuit designers want to be sure to have a robust electrical design that can handle worst case voltages and currents at maximum ambient temperatures. Many times one oft-forgotten area, or an area of lesser concern, is the package's thermal-design integrity under worst-case operating conditions. This may be an even more important area of your design since it determines, in a major way, the reliability of the circuit.

Shown here is a relatively quick and easy way to determine if the design is the best it can be, thermally speaking, without cumbersome or time-consuming methods or expensive software analysis. Also shared are some methods to lower Pd, or at least offload power from the IC package itself.

We hope that you find these methods and tools useful as well as a means to ensure the integrity of your design, allowing you to gain time saved that can be used in other duties in the busy day of an EE.

References

1. D. Edwards, "IC Package Thermal Metrics," June 2007, Application Report, SPRA953A, Texas Instruments.
2. Lohia, Alok, Nov. 11, 2005, TI Thermal Characteristics presentation, Texas Instruments.
3. Quek, Yang Boon, 2006, "QFN Layout Guidelines," Application Report, SLOA122, Texas Instruments
4. Ivins, Tom, May 2006, "Performing Thermal Analysis in System," Power Electronics Technology Magazine

Stephen Taranovich is Global Account Executive and Senior Analog Field Applications Engineer at Texas Instruments. He received his MSEE from Polytechnic University, Brooklyn, New York, and his BEEE from New York University, Bronx, New York. He can be reached at ti_staranovich@list.ti.com.

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