Design Article
Time is right for clockless design
Alan Percy
6/10/2010 9:54 AM EDT
While Moore’s Law has always been theoretically faithful in terms of its continued march forward with transistor density, the complexity of designing to advanced geometries flirting with atomic sizes has resulted in a frustrating paradox: it is not easy to take full advantage of the new nodes because high variations require design margins that limit the intrinsic technology potential.
Today, design engineers must evaluate tradeoffs between power and speed, typically compromising on one or the other. Yet, in an uncompromising consumer market that demands both higher performance AND longer battery life, what to “leave on the table” is a difficult and painstaking decision.
Designers have long sought the Holy Grail of a solution to maximize the performance vs. power trade-off. Fast designs that meet stringent power requirements. The ying and yang of complex IC design.
One such approach that has been looked at for many years as having great promise is asynchronous or clockless design technology. This technique has always seemed to be academically and conceptually a very viable method, but various attempts at making it a commercial success have never gotten traction.
For sure, self timed circuits which do not require any clock signal offer a wide range of benefits:
- Consuming power only where and when needed
- Reduced latency (never waiting for a clock edge)
- Robust to PVT variations (reduced design margins)
- Removal of system level blocks (clock trees, high freq PLLs)
- Operating at very low voltage
And, in fact, these improvements have been validated by multiple projects (industry and academic). So what has held companies back from adopting this approach and delivering chips that leverage its potential?
Despite a sincere enthusiasm, there is often a perception that asynchronous design does not work. This perception comes from a confusion between the validity of the technology and the ability to integrate asynchronous design inside an existing design flow.
Despite this perception, several companies today have been delivering chips based on an asynchronous implementation, showing breakthrough performances in terms of speed/power ratio (e.g. Achronix, Fulcrum, Octasic).
So when you hear “it does not work”, does it really mean “I don’t think I can use it myself”? Admittedly, the gains achieved through the use of asynchronous technology have to date required an extra degree of effort. These early successes have managed to deal with the challenges that have prevented asynchronous from being more broadly adopted, namely:
- How to combine asynchronous and synchronous circuitry on a single chip
- How to use an existing EDA flow, from simulation, through synthesis and timing
- How to guarantee performance
- How to support a timing driven flow with asynchronous technology
- How to test chips, maintain quality assurance
- How to validate on FPGA emulators
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Les Slater
6/14/2010 11:40 AM EDT
Besides tools clockless requires a mindset change. I see the typical engineer as somewhat akin to Dr. Strangelove: burnt in habitual reflexes.
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Antoine Sirianni
6/15/2010 8:35 AM EDT
Design in the realm of silicon based systems is a matter of trade-offs and the envelope is somehow constant for a given technology node. If you put emphasis one hand, you will loose on some other. What is it that you loose designing asynchronous circuits?
Besides, as far as I know, Dr. Strangelove in Stanley Kubrick's movie was inspired from John Von Neumann.
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Les Slater
6/15/2010 12:27 PM EDT
"...the envelope is somehow constant for a given technology node."
In the context of moving to clockless or mixed it seems that the concept of envelope is vague at best. There are obvious trade-offs though. The obvious one is lack of mature tools and experience.
I believe that it will take a totally new look at methodology starting with the definition of the problem space. What do we really need to accomplish?
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Antoine Sirianni
6/15/2010 3:07 PM EDT
There has been a long track of academic research on asynchronous design since 3/4 decades. Some companies like Handshake Solutions (not mentionned in the paper) have delivered mature solutions to the market.
Yet there are less obvious drawbacks than tooling like: the lack of controllabilty (no time preemption, reduced test capability, problems with reset), the cost (extra area, extra nre).
And you still need to build a complete system including sophisticated software...
So up to you ...
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Les Slater
6/15/2010 4:36 PM EDT
Back in â95 or so I had a lengthy discussion with Fred Pollack of Intel about microprocessor architecture. He was pushing long pipelines and fast clocks at the time. The penalties of pipeline flushes were discussed. I suggested that maybe a better use of Mooreâs Law might be to put multiple processors on a single die. His response was that the software industry was nowhere near prepared to effectively use such. That was only 15 years ago. When we got boxed into a technology corner we got serious.
We are yet still at a primitive stage of parallel processing and asynchronous design may be more complex in SOME respects but I think the vision of the promise will bring positive results.
And as for building a âa complete system including sophisticated software...â. Thatâs what the last paragraph of my previous post was alluding to.
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DKC
6/21/2010 5:35 AM EDT
"Clockless needs standard languages"
I worked on the SystemVerilog committee and attempted to add support for asynchronous constructs way back before it went to the IEEE - with no success.
That failure encouraged me to investigate ESL solutions that would support asynchronous design using C++. So ~ 6 years on I have an extended C++ that will support asynchronous design - http://parallel.cc
Good luck with SystemVerilog for asynchronous design - it's not much good for power aware design either.
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p_g
7/16/2010 6:32 AM EDT
Clockless design certainly have a big advantage of low power and mobile computing devices running on battery can gain a lot here.
Since the speed of async design is purely based on process corner of silicon, it helps a lot in binning where fast part can serve great speed.
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Antoine Sirianni
7/20/2010 4:40 PM EDT
I hope you are not going to bin too many of them ;-)
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p_g
7/23/2010 1:55 AM EDT
Antoine, I wish to bin lot of them in high speed bin :) And this is what async design can achieve.
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Antoine Sirianni
7/24/2010 4:46 AM EDT
Should you think you can afford it.
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NatM
9/13/2010 2:30 PM EDT
Octasic has introduced a family of DSPs that are based on asynchronous technology. This white paper shows how asynchronous technology offers a 3x gain in performance per watt. You can read the white paper here:
http://www.octasic.com/en/tech/opus_dsp.php
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