Design Article

Implement a West Bridge for fast-changing mobile architectures

Hussein Osman, Cypress Semiconductor

7/14/2008 12:51 AM EDT

Mobile handsets are becoming multi-function devices converging multiple technologies including features such as internet access, Wi-Fi capability, integrated music playback, GPS navigation, high-quality digital camera functionality, Bluetooth connectivity, and a standard PC-type interface with capabilities for developing and adding programs. As the integration of handheld devices continues, handset designers are increasingly called upon to consolidate audio, video, internet and navigation services onto a single device. As is evidenced by the success of such devices as the iPhone, they must design handsets that access greater memory capacity and faster peripheral interfaces in order to support the increasing amounts of multimedia data being used.

Mobile handset designers already face difficult market constraints affecting size, power consumption, features, and price. The demand for multimedia features requires larger memory and faster connectivity, directly impacting the price and size of mobile devices as well as limiting the range of viable options. The challenge is further exacerabated by the fact that while processor manufacturing process technology nodes change roughly every two years, memory technology changes every six months. As a result, handset designers must balance between creating a stable and mature platform while attempting to incorporate next-generation features requiring larger memory and faster interfaces, all while keeping total size, power and cost under control.

Personal computers saw a similar trend in early the '90s, where the peripherals around PC processors were changing faster than the processor manufacturers could release new processors. Intel's approach to this problem was to create the North and South Bridges to interface the processor to memory and other peripherals. For processor suppliers, these bridges enabled them to address manufacturers' immediate needs while buying them the necessary time to build next-generation processor chipsets. The use of a bridge in mobile handsets--dubbed the West Bridge--similar to the ones used in PCs can provide the right flexibility to designers to achieve fast design cycles while enabling reliable, high-speed interfaces to the latest storage and other peripherals.

Memory and Storage Requirements
The size of a mobile device's internal memory is limited relative to the size of the data to be transferred. Additional memory can be added by introducing SD or MMC to the handset architecture, an attractive option as it introduces only a small cost to the manufacturer compared to adding internal memory.

The choice for internal storage memory for mobile devices is NAND flash due to its low cost per bit, higher density, and smaller size. The NAND controller implementation constrains the type of NAND devices used. The choices are SLC (single-level cell) and MLC (multi-level cell). MLC is becoming more popular due to its higher density at the same price. The majority of mobile processors available in the market today support SLC NAND if they support any NAND. Some devices are also increasing the internal memory and taking advantage of the cost savings of MLC NAND.

All NAND devices require certain overhead on the controller side to maintain and maximize the life span of the device used. The controller has to understand how many bad blocks there are; this is known as bad block management. Some blocks are marked by manufacturers as bad blocks and others will become non-usable over the lifetime of the device. In order to minimize the number of blocks wearing out, the controller can employ wear-leveling techniques which spread writes evenly throughput the storage device. The controller should also manage errors through its ECC state machine. The support level for NAND management is continuing to change with the process technology node, and NAND Flash is one of the fastest changing technology nodes in memories today.

Currently, most mobile device architectures are not taking advantage of all the possible performance and reliability capabilities of NAND Flash, resulting in a reduced user experience. Additionally, densities are increasing as well. Mobile processors, however, are not able to keep up with these changes. Mobiles architectures must therefore adapt to support changing NAND Flash requirements quickly and efficiently if designers are to keep both removable and embedded memory flexible while maximizing performance.


Figure 1. As memory process technology nodes shrink, Error Correcting Code (ECC) capabilities in the Flash controller must increase to maintain data integrity.

Throughput Requirements
Multimedia applications require the ability to handle large amounts of data on both mobile devices and user PCs, given that the PC is typically used for managing the multimedia data to be sideloaded to a handset. Sideloading is commonly done directly between the mobile handset and PC using a USB cable; research shows that approximately 80% of the users who listen to music on their mobile handheld transfer it from a PC to their mobile devices to take on the road. Pictures, videos and games also fall into the same usage model. Becoming truly mobile means the ability to transfer data to mobile devices quickly, as well as having a large amount of memory in the handset to save data onto, in order to guarantee an acceptable user experience.

USB is the choice for communication between the handset and PCs given its stable, well-defined protocol with high data rate. Low-speed USB is used mainly for human interface devices such as keyboards and mice. Full- and high-speed USB are used for data transfers at 12Mb/s and 480Mb/s respectively. Current generation mobile processors have integrated full-speed USB. However, full-speed USB is already insufficient for the large data transfers required to support multimedia functionality.

Designers cannot wait for processor manufacturers to integrate high-speed USB in next-generation devices. Instead, they use a dedicated USB controller to implement these capabilities while awaiting integrated support. Unfortunately, the faster the interface, the greater the burden it places on the main application processor.

One approach for reducing processor load is to add another processor to handle communications with a PC and the management of the NAND internal memory. This comes with the upside of superior performance, but having a second processor negatively impacts price, size, and power consumption. Another alternative is to push users to the cellular network for connectivity and data download. Cellular networks, however, are already congested, and adding large PC data transfers will only put more pressure on them. Additionally, users do not want to incur additional data network access costs, nor do they want to deal with the slow, unreliable nature of wireless connectivity and the complexity of the process when they are already used to directly connecting devices to their PCs. As a consequence, neither of these alternatives succeeds in meeting even minimal user expectations.


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