Design Article

How to characterize surface-mount RF devices

How-Siang Yap, Cecelia Ow, and Mounir Adada, Agilent Technologies EEsof EDA division

4/14/2008 3:32 PM EDT

RF engineers rely on the vector network analyzer (VNA) to measure S-parameters of their RF components for characterization and subsequent design use. One problem in measurement is that these components are often meant for surface mounting and do not connect to the VNA directly. Simple PCB test fixtures are often fabricated to surface mount the device under test (DUT) for connection to the VNA, as shown in Figure 1. However, the test fixture itself introduces parasitics to the S-parameter measurements that must be removed in a process called de-embedding.


Figure 1

This article describes a practical de-embedding process that does not require developing an equivalent circuit model of the input and output feeds to the DUT. Nor does it require the input and output feeds to be symmetrical. You will need a simple linear simulator capable of manipulating S-parameters and S-Y-Z-matrix transformation. Our example uses the Genesys Virtual Network Analyzer software from Agilent EEsof EDA, from which the screen shots were taken.

The De-Embedding Steps, Summarized

1.Build three PCB fixtures, with DUT, open, and short.
2.Measure S-parameters of the open, short, and DUT using your network analyzer.
3.Remove the series parasitics from both the embedded DUT and open fixtures by subtracting the Z-parameters of the short.
4. Remove the parallel parasitics from the embedded DUT by subtracting the Y-parameters of the open from previous step.
5. Obtain the actual DUT characteristics by converting Y- to S-parameters from step 4.

The steps are described in more detail in the following section. A fat low-impedance transmission line is used as the DUT to illustrate the before and after results of de-embedding.

Step 1: Build Three Fixtures with DUT, Open, and Short

Prepare for this de-embedding process by fabricating three test fixtures: 1. The PCB with DUT (shown in Figure 2).


Figure 2

2. The open fixture is the PCB without the DUT mounted, leaving only the transmission lines connected to the input and output ports, as shown in Figure 3. This fixture contains both series and parallel parasitics.


Figure 3

3. The short fixture is the open fixture shown in Figure 3 with the ends of the transmission lines to the DUT input and output reference planes shorted by a row of via holes to ground (shown in Figure 4). The grounded via holes short out the parallel parasitics to leave only the series parasitics.


Figure 4

Step 2: Measure S-Parameter of Open, Short, and DUT
With the VNA properly calibrated, measure the S-parameters of the three fixtures and store the results as "Open_Data," "Short_Data," and "DUT_data." Verify the quality of the short and open measurements by displaying their S-parameters on the Smith chart.

Figure 5 shows the open fixture response. The S-parameters are located at the right open region of the Smith chart. It shows the parallel capacitive parasitics in the open fixture.


Figure 5


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Bhola_#1

8/20/2010 5:41 PM EDT

What would be the accuracy over wide frequency band. This seems like de-embedded S-parameter using TRL kit. I would like to try your approach to get de-embedded S-paramter of RF power amplifier from DC-6 GHz. I have tried TRL but it is very band limited. Also, how to compensate phase of transmission line upto DUT input/output pins.

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