A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies
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Extended scalability of perpendicular STT-MRAM towards sub-20-nm MTJ node
Unveiling the next generation of wireless apps with FRAM-based MCUs
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PCM Progress Report No. 7: A view of Samsung's 8-Gb array
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Design calculations for robust I2C communications
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Memory subsystem validation through real-time compliance test and logic analysis
Pick the right storage solution for each part of the cloud
2D vs. 2.5D vs. 3D ICs 101
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Compliance and conformance: testing to new IEEE standards
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Pick the right SSD drive for the application
RDIMMs maximize server performance, reliability, and scalability
Building a NAND flash controller with high-level synthesis
FPGAs unleash potential of Flash memory for enterprise applications
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Resistive RAM for next-generation nonvolatile memory
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Choosing the right synchronous SRAM for your application
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The Memory Designline is edited by Kristin Lewotsky. Please contact Kristin at