Designing Ethernet links for EMI compliance

Emissions in a system can be traced using a simple model; generated from a ‘source’ and transported to an ‘antenna’ via a coupling route.

Dealing wth the ‘Source’
Interference is usually generated by two sources: the system clocks and power supply unit (PSU). The choice of the MAC-PHY interface will determine the required source-clock frequency; these are usually 25 MHz for MII, 50 MHz for RMII and 125 MHz for SMII interfaces. Selecting an MII interface over the SMII will reduce clock edge-rates; resulting in lower EMI.

Crystal or oscillator placement is critical and should be as close to the devic, with the shortest track length possible. To avoid any harmonic coupling, ensure no other tracks run parallel or underneath the clock source.

The power and ground noise from the power supply should be less than 50 mV peak-to-peak. Increasing the bulk decoupling capacitance can reduce PSU noise. Filtering is essential between the analog and digital V_DD pins. Verify that the power supply is correctly rated for the application, as increased noise will result due to an incorrect rating.

EMI radiation
EMI radiation can be identified as either differential or common-mode radiation. Differential-mode radiation is caused by currents flowing in loops, usually from track layout. It's important to follow standard PCB track-layout recommendations:

• Route differential pairs together, on the same PCB layer, with controlled 50 Ω impedance to ground.
• Keep trace lengths of each differential pair equal.
• Keep all clock and differential pairs at least 3 times the track width away from other traces.
• Keep clock traces as short as possible, avoid loops, minimise stubs and sharp corners.
• Ensure clock traces have an unbroken reference ground plane.
• Terminate clock signals and MII interface bus with series resistor (33 to 50 Ω).
• The optimum resistance can be identified by observing the waveform with a scope, since overshoot will increase EMI radiation.
• Add a 100 nF decoupling capacitor close to each V_CCpin. This will reduce radiated emissions by providing a low-impedance path for high-frequency currents to ground, thereby preventing a significant power-supply loop.

Providing a dedicated ground and V_CC plane will dramatically lower noise over the use of power tracks, by reducing ground impedance and ground-loop areas. Do not split ground into separate analog and digital ground planes for devices such as the Micrel 10/100 Ethernet devices. Place and route the analog components within the analog V_CC plane and, similarly, with the digital components within the digital V_CC plane.

Using magnetic components, such as ferrite beads, and chassis ground will help reduce common-mode radiated emissions and act as a shield to provide ESD protection for PCB components. Figure 1 shows the recommended layout of signal and chassis ground planes.

(Click to Enlarge Image)
Figure1: Recommended PCB layout of signal and chassis ground planes.

The chassis ground should be present on all PCB layers except the power layer(s), connected together with super vias. Connecting the chassis ground at multiple points to the external chassis or metal frame will enhance ESD protection. Transformer selection should ensure that integrated common mode chokes are present in both receive (RX) and transmit (TX) paths.

Conclusion Understanding the basic interference mechanisms and following easy design techniques will ensure that Ethernet design is made simple for EMI compliance. Vendors such as Micrel also provides evaluation boards, reference schematics and Gerber files for all their Ethernet devices, enabling faster time-to-market, Reference 1.

References
1. Micrel Application Note 111, General PCB Design and Layout Guidelines

About the author
Mike Jones is a senior field applications engineer at Micrel Inc., San Jose, CA.