How to improve signal integrity in Rapid IO serial interface designs

High speed serial links between chips are now being adopted for a wide variety of applications in order to improve the throughput with a narrower bus width. Some of the latest DSPs and processors, for example, are being introduced with serial RapidIO.

For many hardware designers, inter-chip communication using bus speeds over 300MHz is a new challenge they have not yet faced. Furthermore, the design of a high-quality data link operating at GHz data rates requires more care and understanding to ensure that performance is not impaired by the effects of board layout and noise.

This article explores SI challenges and considerations that the designer must face, and aims to provide a practical guide to overcoming these challenges. This includes recommendations for the successful placing, routing and decoupling of the device on a PCB. A 16-port serial RapidIO switch is described, providing a practical example of how these principles may be applied.

Signal quality
The quality of a signal is important at all points within a system, and in serial RapidIO is quantified by the size of the receive eye. The eye is an infinite persistence trace where the waveform is repeatedly traced over the previous trace (Figure 1, below).

Figure 1: Typical overshoot and undershoot characteristics on a pulse

There are many opportunities for the signal quality to be compromised: by the introduction of noise or other random signals onto the signal path, by poor signal trace routing, by means of either conduction or radiation from external sources or by generation within the system itself. All of these factors combine to shrink the receive eye. The areas that need to be considered include:

: Power supply input to the board, outputs of local regulators and distribution
Clock generation and distribution
Decoupling
PCB substrate material
Chip-to-chip connections
Board-to-board and backplane connections
Board stack-up and impedance control
Inter-rack connections, cable and connectors

When working at frequencies above 300MHz, the majority of design best practices that are used for board layout at lower frequencies need to be revised. It is necessary to account for factors that arise as the wavelength becomes comparable to the board dimensions.

This applies not only to the wavelength of the fundamental frequency but also to the Fourier components that make up the complete waveform. FR4 material may still be used successfully as a substrate, but the permittivity of the material and the dissipation or loss factor needs to be considered at higher frequencies.

Figure 2: Scope trace containing an eye diagram

Through-hole via design also becomes important because unused barrel length, which has a negligible effect at lower frequencies, presents an impedance mismatch in thicker boards and backplanes. The performance of post layout simulation is desirable in order to draw attention to routes of less-than-ideal SI and point out areas of crosstalk.

Particular challenges in terms of on-board SI are created by the presence of a high-speed processor bus, high-speed memory interface, by clock generation and clock noise, and various sources of board noise such as ground bounce, crosstalk etc. Sources of noise can typically include:

Single-ended parallel buses: switching noise can result from current transients necessary to charge/discharge all the lines.

Power distribution: inadequate power distribu¬tion aggravates the noise dilemma, particularly if there is inadequate copper for the current demands, or inadequate or improperly positioned decoupling.

Impedance matching: improper impedance match¬ing results in reflections that can cause overshoot, undershoot and ringing on the signal lines that make up the differential pair (Figure 2, above). This results in a reduced receive eye and increased jitter in the signal. The fol¬lowing items are the main causes for mismatch arti¬facts being introduced onto a signal, such as (1) changes in routing layers, and, (2) poorly designed escape routing from the device.

Ground bounce: this causes input thresholds to change and can lead to cor¬rupt bits. Serious cases can cause device latch-up, with power cycling required to recover from it.

Crosstalk: this is caused by the close proximity of traces belonging to different signal groups. The result of crosstalk in a serial communication link is closure of the receive eye due to the imposed jitter. Crosstalk is caused by (1) insufficient track spacing to other signals and (2) poorly implemented serpentines for path length matching. This causes edge advancement as part of the signal takes the short path (jumping legs of the serpentine) while the main signal takes the long path.

Clock generation: both clock generation and clock buffering can become noise generators unless careful attention is paid to details such as EMI filtering components and minimizing crosstalk.

Manufacturers' layout guidelines must be followed in order to obtain the highest quality clock signals from the device. The consequence of a poorly-implemented clock is jitter in excess of that required by the RapidIO device resulting in poor throughput performance (evidence of which is seen in high bit error rates at the receiver).

Precautions
How can the designer ensure that these effects are kept under control? First of all, by adequate trace isolation between syn¬chronous signal groups, and by restricting track lengths and minimizing skew between the signals of a differential pair. Routing should be carried out with a view to limiting parasitics by minimizing the number of layer transitions.

Vias are costly in unwanted inductance and stray capacitance and should be kept to a minimum. Usually, two vias per trace is the maximum allowable in addition to the BGA pads.

Choosing the right switch can help to meet the high-speed challenge, while more generally good design practices can help board designers take control of signal noise resulting from board level traffic. Some of these design features help in limiting external noise sources, while others are needed to address noise at the device itself. A properly designed package that minimizes parasitics is one of the first considerations, as is the positioning of power and ground pins.

Clock generation
Clock generation circuitry requires particularly careful attention to detail, especially in terms of layout, proper termination and the judicious use of EMI filtering components. The impedance of the traces must also be controlled to avoid unwanted reflections. Improper application of these principles can result in clock generators becoming noise generators. Clock generation and buffering can also lead to unnecessary noise, because of the increased design complexity and the introduction of routing voids in the power and ground planes.

Pins and packaging
In component package design, it is crucial to use a sufficient number of power and ground pins as well as placing and partitioning them correctly. An inadequate quantity of power and ground pins will increase the return current path length, which can lead to chip core supply instability and increased electromagnetic noise. Improper power and ground pin placement can also negate a decoupling strategy .

The pins need to be properly placed in order to allow decoupling to be located directly under the package, with minimal trace length to control inductance. Partitioning of core logic power and ground from I/O power and ground is also critical to controlling noise.

From the perspective of device manufacturing cost, wire bond packaging may appear to be an attractive option, but from an SI and system reliability standpoint, flip-chip mounting offers far more advantages. It allows for ample power and ground connections, even for a high signal count package, and power and ground bumps can be used to surround sensitive I/O bumps.

With wire bonding, the number of pads is limited by the outer perimeter, so a high signal count package leaves very little room for power/ground connections and necessitates fewer and longer current return paths. The use of solder bumps rather than wires greatly reduces parasitic inductance, since bumps represent much shorter and thicker connections than wires (Figure 3, below).

Figure 3. Flip-chip BGA packaging gives much lower parastics than wire bonding

The length of bond wires also greatly increases the susceptibility to crosstalk, and imposes slew rate limits on the signal. Using a BGA package allows the signal and ground connections to be interspersed in a "checkerboard" arrangement, to effectively shield the signal lines from interfering with each other.

Cables and connectors
Only cables and connectors specifically designed for high frequency and GbE applications should be used for connecting high bit-rate systems. Use of inappropriate, unshielded or poorly-matched cabling can cause unwanted reflections and pick up interference in a similar way to that described for on-board discontinuities. Proprietary types of cable for these applications are availably from a variety of manufacturers including Tyco Electronics, Molex and WL Gore.

Transmission line
The impedance requirement of the serial RapidIO interface is 100 ohms. In order to main¬tain this consistent differential impedance, the options for the construction of the transmission line are limited to either strip¬line or microstrip.

Microstrip is used when the signalling must be routed on an outer layer of the board, while stripline allows the signalling to be placed on an inner layer where shielding by adjacent power and ground planes is possible. Edge-coupled differential (or coplanar) stripline, rather than a broadside coupled or dual stripline, is recommended.

Edge-coupled differential stripline is shown in Figure 4 below, along with the equations for single-ended and differential impedance. The stripline is symmetrical when h1= h2. The minimum recommended layer count is six and the optimum design has 16.

Figure 4. Block diagram of Tsi568A serial RapidIO switch interfaces

The signal return path is particularly important, and is defined as the route that current takes to return to its source. This may be through ground planes, power planes, other signal paths and through ICs.

The current always takes the path of least resistance. A simple way to evaluate the integrity of the return path is to draw a loop tracing the current from the driver through the signal conductor to the receiver - the smaller the area of the loop, the lower will be the parasitic inductance.

The following design rules apply to all return paths:

Always trace out the return current path and provide as much care to the return path as the path of the signal conductors.
Do not route impedance-controlled signals over splits in the reference planes.
Do not route signals on the reference planes.
Do not make signal layer changes that force the return path to make a reference plane change.
Decoupling capacitors do not adequately compensate for a plane split.
Do not route over via anti-pads or socket anti-pads.

If reference plane changes must be made, try to follow the following recommendations:

Change from a VSS reference plane to another VSS reference plane and place a via connecting the two planes as close as possible to the signal via. This also applies when making a reference plane change from one VCC plane to another VCC plane.

For symmetric stripline, provide return path vias for both VSS and VCC.

Do not switch the reference plane of a signal from VCC to VSS or vice versa.

Guard traces - tracks that run parallel to a signal trace and are connected to the ref¬erence plane - may be used to minimise crosstalk, but they take up board space and will be required to be "stitched," or connected with vias, to the reference plane at intervals that prevent resonance.

Due to the high-frequency content of the serial RapidIO signals, it is necessary to minimize the discontinuities imposed by crossing ground and power planes when it is necessary to transition to different signal layers. The use of a controlled impedance via is desirable.

Summary
With some forethought, and a knowledge of the basic design rules, it is possible to apply high-frequency interconnects such as RapidIO to a system without encountering any of the problems that are traditionally associated with poor SI, such as noise, transient effects or crosstalk and jitter.

If traces and signal paths are kept as short as possible, are either shielded by ground planes or kept physically separated from each other, and if care is taken to avoid mismatched impedances or any configuration likely to support resonance, good SI is easily achievable. The moral of the story? It is always simpler to avoid SI problems in the first place - by creating a well thought-out design verified by simulation - than to try and correct SI issues in a problematic design.

Andre Pirnat is senior applications engineer at Tundra Semiconductor.