Using IEEE-1588 transparent clocks to improve system time synchronization accuracy

Key to understanding synchronization is that clocks drift and need to be corrected periodically. This begs the questions, "How long are they 'the same' before they are not 'the same' as they drift apart?"

It takes time to go through the process of correcting the time, and during this process how accurate can we set the time relative to another clock in the first place? This process of correcting the time is challenging and is a limiting factor in how accurately two clocks can be synchronized.

IEEE-1588 defines a process of transferring time. However, before jumping in and demonstrating that Transparent Clocks (aka IEEE-1588 enabled switches) work great to improve IEEE-1588 time transfer accuracy, there are a few fundamentals we need to cover along the lines of offsets and delays and how switches and routers contribute to both.

Offset & Path Delay
The difference between the time on two clocks is known as an offset. In timekeeping we strive to keep the offset below a particular value so that we can assign an accuracy value to the clock.

The process of setting one clock to another is a matter of computing the offset, say between the slave clock and the master clock. Low accuracy applications simply broadcast out the time from the master and the slaves set their clocks when they receive it.

This is analogous to days past when the town bell rang at high noon (the on-time "event") and we were not concerned with how long it took the sound waves to reach our ears or how long it took as we set our clocks. That time it takes for the time event to travel from the master clock to the slave is called delay, or path delay (Figure 1 below.

Figure 1. Timing messages sent from the master to the slave (and vice versa) experience variable delays caused by the switches in the network leading to timing errors at the slave clock.

Symmetric & Asymmetric Delay
Time transfer delay and errors associated with eliminating delay are the main source of error related to accurately transferring time from one clock to another. In packet based networks such as Ethernet, timing packets are exchanged between the master and the slave for the purpose of computing the time offset.

If the packet exchange delay on the master-to-slave path and slave-to-master path were identical, the offset could be computed perfectly since the delays would cancel out in the math. The notion of path delay both ways between the master and the slave being the same is called symmetric delay and time transfer over packet networks assumes symmetric path delay.

Unfortunately, path delay does vary between the master-to-slave and slave-to-master and this is called asymmetric delay. To make it worse, these asymmetric delays introduced by the network cannot be easily characterized so the whole problem is dubbed nondeterministic. IEEE-1588 timing packets transit a LAN containing switches (or worse routers) that add asymmetric delay in the 10's to 100's of microseconds, if not more.