Design Article

Firmware architecture in five easy steps

Michael Barr

9/21/2009 4:03 PM EDT

Over the past few years, I've spent a large amount of my time consulting with and training software development teams that were in the midst of rearchitecture. These teams had already developed the firmware inside successful long-lived products or product families. But to keep moving forward, reduce bugs, and speed new feature development, they needed to take the best of their old code and plug it into a better firmware architecture.

In the process, I've collected substantial anecdotal evidence that leads me to conclude that few programmers, technical managers, or teams truly understand what good firmware architecture is, how to achieve it, or even how to recognize it when they see it. That includes the most experienced individual developers on a team. Yet, despite the fact that these teams work in a range of very different industries (including safety-critical medical devices), the rearchitecture process is remarkably similar from my point of view. And there are numerous ways that our clients' products and engineering teams would have benefited from getting their firmware architecture right from the beginning.

Although learning to create solid firmware architecture and simultaneously rearchitecting legacy software may take a team months of hard work, five key steps are easily identified. So whether you are designing firmware architecture from scratch for a new product or launching a rearchitecture effort of your own, you can use this step-by-step process to help your team get started on the right foot.

Step 1: Identify the requirements
Before we can begin to (re)architect an embedded system or its firmware, we must have clear requirements. Properly written requirements define the WHAT of a product. WHAT does the product do for the user, specifically? For example, if the product is a ventilator, the list of WHAT it does may include a statement such as:

"If power is lost during operation, the ventilator shall resume operation according to its last programmed settings within 250 ms of power up."

Note that a properly written requirement is silent about HOW this particular part of the overall WHAT is to be achieved. The implementation could be purely electronics or a combination of electronics and firmware; the firmware, if present, might contain an RTOS or it might not. From the point of view of the requirement writer, then, there may as well be a gnome living inside the product that fulfills the requirement.1 (So long as the gnome is trustworthy and immortal, of course!)

Each requirement statement must also be two other things: unambiguous and testable. An unambiguous statement requires no further explanation. It is as clear and as concise as possible. If the requirement includes a mathematical model of expected system behavior, it is helpful to include the equations.2

Testability is key. If a requirement is written properly, a set of tests can be easily constructed to verify that requirement is met. Decoupling the tests from the particulars of the implementation, in this manner, is of critical importance. Many organizations perform extensive testing of the wrong stuff. Any coupling between the test and the implementation is problematic.

A proper set of requirements is a written list of statements each of which contains the key phrase " the [product] shall ..." and is silent about how it is implemented, unambiguous, and testable. This may seem like a subject unrelated to architecture, but too often it is poor requirements that constrain architecture. Thus good architecture depends in part on good requirements.3


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mellowdog

9/22/2009 11:51 AM EDT

Great article, Michael.
But, I disagree with some of your statements in step 2. The statement "The system architecture diagram identifies data flows and shows partitioning at the hardware vs. firmware level." is not correct, IMO, for the architecture - especially if it is to stand the test of time. In fact, endnote 2 seems to also disagree - "a mathematical equation may be converted into a look-up table plus interpolations, which may be executed by either hardware or software (or by a gnome)."
I believe that the architecture should be implementation agnostic. It could be n processors, m FPGAs, 1 ASIC/FPGA, or ??. It is possible that on the day of initial release, the architecture indirectly 'infers' a particular hardware/firmware implementation based on the reader's 'known state of the art' but it should in no way prescribe any design elements such as hardware/firmware division.

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riceman0

10/11/2009 1:56 AM EDT

Mellowdog, my gut reaction is to disagree, I see the hardware/firmware division as probably the foremost architectual decision. In contrast, whether you choose a gnome or lookup table is unlikely to affect architecture.

But I'd like to understand your perspective better. If an architecture isn't at least deciding where the hardware/firmware division is, then what *is* it deciding?

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jesup

10/28/2009 11:28 AM EDT

I agree with mellowdog - the decisions of what's hardware and what's firmware is design, not architecture. The architecture often is influenced by the known or expected hardware, but the architecture shouldn't care if hardware handles the filtering of a DAC or if it's handled in firmware with a simpler hardware DAC, etc. (Semi-valid off-the-cuff example). Some of those decisions (i.e. whether to use a bit of the hardware) might even wait until implementation.

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krwada

11/9/2009 7:55 PM EST

This is a good article. However; one of the main assumptions here is that people generally know what they want and are able to clearly and succinctly specify their desires.

In reality, it is usually a bit more muddled.

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KarlS

11/11/2009 1:32 PM EST

Step 3, figure 1, There's my focus. There are many micros available, but still a lot has to be done in HDL because of the real-time demands even though it would be desirable for the processor to do them. Those micros all have similar structure(architecture?) with different instruction sets. So a compiler converts C to machine code which has the "von Neumann bottleneck" because instructions and data are in the same memory and only one can be accessed per cycle. My project solves this problem.
I expect to be ridiculed and whatever, but I will start a thread because I think enough is done to be defensible.
Thanks for bringing out the point.

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DrOctavius

11/27/2009 2:06 PM EST

krwada,

Good and very important point.

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