The ITRS process roadmap and nextgen embedded multicore SoC design

The semiconductor technologies that will be required can be broadly categorized into three categories: "Moore" " Geometric Scaling; "More Moore" " Equivalent Scaling and "More than Moore" functional diversification " all of which will have significant impact on the embedded networking space with new Systems on chip architectures that make extensive use of

1) Multi-Core (MC),
2) Cache hierarchy,
3) On-chip fabric,
4) On demand Accelerator Engine (AE), and
5) Connectivity,

all engineered to provide a scalable, software-based Multi-Core/Accelerator Engine SoC (SOC-MC/AE) solution that targets a wide range of applications from ultra low-end to high-end that preserve & extend the user experience through new services.

Figure 1. Macro trends for cellular technology.

The three "Moore's"
While technologies and structures push the limits of Moore's Law and productivity, the ITRS initiated the concept of "More Than Moore," which first appeared in the 2005 ITRS publication, calls for the integration of Functionality that does not scale. It is mostly analog functionality, but also includes passives, high voltage, sensors, actuators and enablement.

During the ITRS summer conference, an overall definition was introduced grouping three aspects of "Moore" concept:

Moore: Geometric Scaling
More of Moore: Equivalent Scaling
More Than Moore: Functional Diversification

While "Moore's Law" is mostly focused on geometric scaling in continuing shrinking of horizontal and vertical physical feature sizes of the on-chip logic and memory in order to improve density (cost per function reduction) and performance (speed, Power) and reliability values to the applications and end customers.

"More of Moore" is about equivalent scaling which occurs in conjunction with, and also enables, continued Geometrical Scaling plus non-geometrical process techniques that affect the electrical performance of the chip. The third element is "More Than Moore" is about functional diversification.

The "More Than Moore" refers to the incorporation into devices of functionalities that do not necessarily scale according to "Moore's Law," but provide additional value to the end customer in different ways.

The "More-Than-Moore" approach typically allows for the non-digital functionalities (e.g. RF communication, power control, passive components, sensors, actuators, 3rd party IP/ennoblements) that to migrate to system board-level/particular package level (SiP) or Chip-Level (SoC) potential solution.

There is increasing tendency to have more functions on a chip which are not scaling according to the same pattern [as defined in Moore's Law]. This is functional diversification rather than scaling, but it's part of the same business and same technology.

The combination "Moore's Law" and "More Than Moore" enables the creation of system-on-a-chip and system-in-a-package and, as such, adds value to systems rather than just integrating more of the same functions on a chip.

Functional diversification in SoC design
The ITU-R is currently studying user demand predictions in future systems such as the amount of traffic in the year 2010 onwards in calculating required spectrum bandwidth for the future development of IMT-2000 and IMT-Advanced.

The IMT-2000 (International Mobile Telecommunications) systems are 3rd generation mobile systems, which provide access to a wide range of telecommunication services, supported by the fixed telecommunication networks (e.g. PSTN/ISDN/IP), and to other services which are specific to mobile users. Among the key features of IMT-2000 are:

1) Capability for multimedia applications within a wide range of services and terminals
2) High degree of commonality of design worldwide
3) Compatibility of services within IMT-2000 and with the fixed networks
4) High quality
5) Worldwide roaming capability, and,
6) Small terminal suitable for worldwide use

The next 5-15 years will also mark trends towards:

1) Scalable networks that deliver high rich multimedia content at broadband speed anywhere and anytime and on any device;
2) Markets in which the consumer will play a major role in creating high rich multimedia content;
3) Emergence of advanced IP-based applications and services that drive high bandwidth scalable networks;
4) Complex multi-processing platforms equipped with multi-core/multi-threading and accelerators that support advanced applications and services;
5) Advancement in process technology from 65-45-32, 22 and sub 10nm technology
6) Scalable encryption and antivirus everywhere in the network;
7) Home networking will be a complex network converging data communications, entertainment;
8) Seamless mobility in the home, in the office/vertical market, on the road

In contrast with PC & Server Applications, and due to the fundamental difference between core speeds and memory/IO latencies, today's embedded processor architectures are unable to deliver meaningful performance for the connected computing scenarios outlined earlier.

Nearly every commercially available integrated general-purpose processor shipping in volume today is designed using a single-threaded architecture, which is performance and application limited by today's standards. As applications are becoming more and more network-centric, this legacy processor design approach fails to address the throughput requirements of today's converging compute and networking paradigm.

This evolving packet-oriented environment is characterized by high memory access latencies, which are not effectively managed by conventional processor architectures. This weakness can severely impact processor performance and workload efficiency. When a memory access cannot be serviced immediately and no additional instructions are ready to be executed, conventional processors stall and waste valuable processing cycles.