Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3

Recall that if the clock jitter specifications are violated, the clock jitter's adverse effect on the input timings can be neutralized by increasing the clock period. This suggests that the clock jitter value itself is not the issue; the issue is how much the input timing is adversely affected by the clock jitter.

Also as previously mentioned, until a statistically sound standard deviation (sigma, s) value for the clock jitter is obtained, the clock jitter investigation is incomplete. A statistically sound standard deviation value depends on two factors: (1) the sample size used to measure the clock jitter; and (2) the system BER target.

When investigating clock jitter statistically, only the negative clock jitter only needs to be looked at. For device functionality concerns, the DRAM is adversely affected by negative clock jitter violations, not positive clock jitter violations.

And when the output timings are evaluated, the positive clock jitter results should mirror the negative clock jitter results. Additionally, since the clock jitter is Gaussian, all the clock jitter values should track each other. Analyzing ^tJITper and how it is compensated for generally ensures that the other clock jitter specifications will not be an issue.

Clock Jitter Sample Size and Standard Deviation
From past experience, most if not all clock jitter samples are evaluated without any regard for sigma. After inquiring, it was generally found that the clock jitter values were acquired with enough samples to yield a clock jitter value that was about 3 or 4 sigmas. For example, if ^tJITper MIN was measured to be "120ps, then a sigma in the range of 4 would not be unexpected.

This would mean that sigma is about 30ps. Experience has shown that until enough clock jitter samples are acquired to obtain a ^tJITper MIN value that is 6 sigma away from the nominal clock, or tCK(avg), not enough samples have been acquired to obtain a reasonably stable sigma.

Using the previous 3ns DDR2 SDRAM (DDR2-667) example with the measured ^tJITper(MIN) of "120ps and 30ps sigma, it would appear the ^tJITper(MIN) limit of "125ps is not violated and the system is good to go. Even then, considering that clock jitter is random and results in a Gaussian distribution, a 4-sigma clock jitter means almost all of the clock periods are within specification. Less than 0.1% of the clock pulse widths will be lower than specifications allow, as shown in Figure 6 below.

Figure 6: 4 Sigma tJITper Example

BER Targets
Although the previous clock jitter analysis examples seem to provide a positive outcome; further study actually reveals the measured clock jitter is predicting a noticeable potential for failure. The reason it is a "potential failure rate" is because the clock jitter analysis is only identifying clock timing errors and not all clock errors result in a DDR2/DDR3 functional failure.

The analysis does not go far enough because it didn't determine what the system BER target is and how well the clock jitter would respond to it. Applying DDR2-667 to clock jitter with ^tJITper(MIN) of "120ps and a sigma of 30ps, approximately one clock out of every 31,574 clocks will have one clock period less than the minimum allowed at DDR2-667, as shown in Table 3 below. This means the clock period will be too small once every 94,700ns, or 94.7 microseconds.

Table 3: Standard Normal Distribution Probabilities: BER at DDR2-667, 4 Sigma

If the initial clock jitter analysis stopped with the measured ^tJITper(MIN) of "120ps and ignored the sigma, it would be the same as saying the system is allowed to have a BER of 4 sigma, resulting in a minimum clock period violation once every 94.7 microseconds.

The system BER for clock period violations due to clock jitter must be defined before a thorough clock jitter analysis can be completed. DDR2/DDR3 have a defined SER, which means the DRAM will fail once in awhile. Since the DDR2/DDR3 SER rate is so low, the defacto BER for SER events is extremely high and is ignored.

Clock timing has also had a high defacto BER for clock jitter related violations; however, as clock speeds have increased, clock jitter has become a large enough percentage of the clock period that it should no longer be ignored.

All memory systems do not require the same BER for clock jitter, but surely something more than 4 sigma is required. Six sigma is often used as a good quality target.

With the ^tJITper(MIN) 6 sigma measurement equal to the ^tJITper(MIN) specification limit, a probability of one clock period violation due to ^tJITper(MIN) will occur once every 3.04s, as seen in Table 4 below. Such a low BER is unlikely to satisfy most memory application needs.

Table 4: Standard Normal Distribution Probabilities: BER at DDR2-667, 6 Sigma

BER targets need to be much higher. BER targets in the range of 10 to 11 sigma should satisfy most memory application needs. (Table 5 below.) A BER target of 10 sigma translates to a ^tJITper sigma of 9"12ps for DDR2 and 7"10ps for DDR3.

Table 5: BER at DDR2-667 with 10,11 Sigma Targets

Take the previous example of ^tJITper(MIN) of "120ps with a sigma of 30ps. A BER of 4 sigma or 6 sigma is not acceptable for almost any memory system. A BER of 10 sigma may be acceptable since the clock violation is only once every four months of continuous clocking.

At 10 sigma, the clock period can be expected to be violated by 175ps (10 * 30ps - 125ps). So, instead of the initial clock jitter analysis suggesting the clock jitter was within specifications, it should show that the clock period ^tCKavg should be increased 175ps to ensure a satisfactory BER for clock jitter effect and acceptable DDR2/DDR3 functionality.

Conclusion
DDR2/DDR3 clock jitter is commonly misunderstood. It is extremely important to analyze clock jitter both when the DLL is locking and when it is locked. When the DLL is locking, the cycle-to-cycle clock jitter must be kept very low. Once the DLL is locked, the DRAM is fairly insensitive to cycle-to-cycle clock jitter, but the clock period jitter and half-period clock jitter need to be analyzed.

It is extremely important to obtain the clock period clock jitter's sigma when measuring clock jitter. Without knowing the sigma, it is impossible to know if the measured jitter value is acceptable.

Once the clock jitter is measured and a statistically sound standard deviation is obtained, clock jitter violations can be neutralized; that is, the clock jitter may violate specifications but it can still be allowed if the timings are adjusted to account for the additional error.

To read Part 1, go to "Defining Clock Jitter."
To read Part 2, go to "DDR2/DDR3 Functionality."

Scott Schaefer is a Senior Applications Engineer for Micron Technology's DRAM group. Mr. Schaefer joined Micron in 1989 and has spent his Micron career focused on the field of DRAM applications. Prior to Micron, he worked for Synertek and IMP. Mr. Schaefer has over 25 years of experience in the electronics industry and has over 50 DRAM-related patents.