Design Article
How to reduce memory power in SoC designs
Anmol Mathur, CTO, Calypto Design Systems and Lisa Minwell, Director Technical Marketing, Virage Logic
10/15/2009 9:18 PM EDT
Removing redundant memory accesses and utilizing the low power modes in embedded memories requires sequential analysis of the design across multiple pipeline stages. Many RTL designs have significant room for memory power reductions due to non-local observability or stability conditions that are very hard for designers to account for manually as well as time consuming to verify them.
Unlike regular design registers that only dissipate dynamic power when they are written, memories dissipate dynamic power when they are either read or written. As such, removing redundant reads or writes can result in significant dynamic power reduction. We discuss sequential analysis techniques used to accomplish this in this paper.
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