Design Article
Minimizing Power Consumption in RTL Designs Using Sequential Clock Gating and Low-Power Synthesis
Venky Ramachandran
5/26/2009 9:42 AM EDT
The combined flow of automated, sequential RTL power optimization tightly linked to low-power synthesis provides designers with a highly efficient, single-pass, low-power design flow.
An automated low-power design flow has been developed by Calypto Design Systems and Cadence Design Systems which combines the automated RTL clock gating of PowerPro CG from Calypto with the low-power synthesis of Encounter RTL Compiler from Cadence.
Read the entire article here.
|
|
|
|
|
Navigate to related information
