Opportunities in Analog Verification

Normally speaking, these things should never happen and a chip must be verified for all these factors before tapeout. Usually, the circuit designers do this in the analog domain. However, these days an increasing demand for specialized verification engineers has been noted in the industry. The reasons primarily being the increasing complexity of block interactions that will cause "accidental" goof-up in connections or logic, and an alternate mindset and skills needed to do the job.

Verification engineers have to be capable of thinking beyond a particular block and formulate their verification strategies in the context of the complete system. Also, verification engineers must be able to abstract a system to the simplest form needed to conduct the tests. Programming skills, scripting and little bit of design skills go a great deal in forming a strong verification engineer. There are different aspects of system verification -- performance and functional.

Performance verification is to verify if the block matches all the numbers from an objective specification document. In case of RF systems this can be compression points, matching, distortion, gain, noise figures, etc. Analog systems might have specifications like gain and noise figure. Whatever these may be, the designers usually do an excellent job in making sure their block meets the required performance. They run their circuits on Process, Voltage and Temperature corners and use different transistor models to characterize the performance of their circuits to the death. However, most of them find it hard to think beyond their blocks. The best block in the system will not do any good if the chip fails to power up. Also, a block like Programmable Gain Amplifier (PGA) might have an eight bit digital control that sets the gain. It is important the effect of all the 256 values. Most of the times, the designers cannot get to this because it is not feasible to run 256 transistor level simulations for testing gain modes when the deadlines force to work on other "important" things.

The verification engineer mindset should be different and they should be told that their only job is to find faults or cases that break a design. As mentioned above, these are functional verification tests. Hardware Description Languages (HDL) like Verilog-AMS helps a great deal in this challenging task. Using the HDL, the most complex blocks can be abstracted to represent its functional behavior with few lines of code. Assertions (error checking conditions) can be included in these models. These assertions perform beautifully in flagging any error. For instance, assertions can used to pull the output of a block to ground if the block is not powered on or if the bias conditions are not in the proper ranges or even if the digital inputs seen by the block are not expected values. This will break the signal path's functionality and thereby make issues like connectivity, incorrect power supplies, and improper biasing standout. Unless a chip passes the final functional verification, it cannot be taped out.

Presently, specialized staffing for analog verification is hard to find. Hence, automating some of the aforementioned tasks and tool support will play a big part in how this process evolves. It is a normal belief in the industry that for every five design engineers, one modeling and verification engineer is required. However, this rarely happens. While this concept is just starting to get popular, verification engineers today typically support anywhere between 10-20 designers. This is a hard task. The EDA companies have already realized this opportunity and incorporating automatic HDL model generation capabilities in their tools (the latest release of Virtuoso from Cadence is an example). However, the effort is still akin to going after the low-hanging fruits than solving the bigger issues. I will present more on this issue later.

One issue that presents a formidable challenge to analog verification is the lack of a framework for top down design. Top down design has been effectively used in digital design flow for over a decade. The quality of initial tapeouts in digital design is way superior to their analog counterparts.

A top down design flow for analog designs would take the following steps:

• Define project guidelines or rules. These rules range from voltage domain information to pin naming conventions. The naming conventions, if followed correctly will make the verification easy after integration of all the blocks.
• Form a hierarchy of the complete analog chip at least until the top level description (or schematics) of core blocks. For instance, in a wireless receiver system, this might mean deciding architecture, blocks and IPs to be used (both new and from existing work), determine the connectivity and floor plan. If it is a heterodyne receiver, what sort of LNA are we looking at, what should be the linearity of the mixer, etc.
• If the chip uses digital control and has local registers, floor plan them and define the digital control modes using a Finite State Machine (later modeled using a HDL like Verilog).
• Write behavioral models for all the core blocks. Using any form of HDL that is suitable (Verilog-AMS, Verilog-A, SystemVerilog, etc) to create these behavioral models.
• Simulate the complete signal path. Once the chinks have been worked out and architecture formalized, start transistor level design for the core blocks.

About the Author:
Saranyan Vigraham is a Senior Engineer with RF Analog group at Qualcomm, Austin. He holds a master and a PhD in Computer Engineering from Wright State University.