Embedded developers should embrace FPGAs

Today, the advent of high-capacity, cost-effective programmable devices holds the promise of a similar advance in the approach to electronic product design through the opportunity to define the system hardware itself in the soft realm. Large scale devices such as high-capacity FPGAs are ideally suited to meet this need and are commonly used to encompass large parts of a system's peripheral logic blocks, including bus interfaces, I/O blocks and even memory. Moving mass logic into the FPGA realm in this way has a profound effect on how hardware is developed and has opened the door to a new era of 'soft' design " one that offers unprecedented levels of flexibility, combined with the potential for large reductions in board real estate and complexity.

While this has the potential to revolutionize the electronic product development process, most embedded software developers still tend to work just as before " selecting a discrete hardware processor at the beginning of the design cycle, creating the physical platform then writing the software to make use of this platform. This lack of exploitation of 'soft' hardware in embedded systems development can largely be attributed to the lack of tools to allow C programmers to use their skills at the programmable hardware level. Indeed most current FPGA design flows are largely derived from those used in the chip design realm and require a very specialized skill-set.

Taking soft design to the next level
Intriguing possibilities open up for embedded developers when the programmability of FPGAs is harnessed to provide what is essentially an abstraction layer on top of the processor – an abstraction layer implemented not only in software, but in hardware as well. Consider a system where the processor is connected to its memory and peripherals through a piece of configurable hardware – essentially a hardware wrapper – that abstracts the processor interface. By simply reprogramming the FPGA to change the hardware wrapper, the system designer could change one processor for another and even move between hard or soft processors without having to modify the rest of the system hardware. From a system perspective all processors would look the same, simplifying the hardware design process. Of course, extending this to the application software would also require compilers that provided C-level compatibility between the processors.

The advantage of such a system is that the processor choice would not need to be made up front. The system could be developed using one processor, but moved to a faster device if, during development, it was found that more performance was needed. Thanks to the wrapper layer, that processor could be soft, hard or even a hard processor core within an FPGA, without impact to the surrounding hardware. The translation layer simply creates a standard interface to the connected peripherals. Indeed the connection of the peripheral devices themselves can be abstracted in the same way.

With this scheme, the FPGA effectively becomes the system interconnection structure, providing universal connectivity for all parts of the embedded system. In other words, it effectively becomes a standard interface 'backbone' that allows both hardware and software to talk to processors and peripherals with universal ease.

Ultimately, the introduction of a transparent wrapper layer above the processor creates an FPGA-based development environment that offers true processor independence. Both software and hardware development is accelerated, processor choices can be made far later in the design cycle and the opportunity exists for efficient software/hardware co-design.

Moving between software and hardware
An extension to the idea of creating processor and peripheral wrappers in configurable hardware is the idea of automatically generating application-specific system hardware to enable software algorithms to be executed in hardware " a sort of 'roll your own' hardware co-processor, if you like.

While the idea of generating hardware directly from C code is not new, until now the approach has been to attempt to allow the complete system hardware to be created using a C-like language. In essence this is not much different to designing FPGAs using a HDL like VHDL or Verilog and requires software developers to learn and adopt new design methodologies. To be truly useful to embedded developers the process must be made transparent. The design tools must take standard ANSI C code input and be able to convert any functions selected by the programmer into hardware. Not only that, but the system must generate all the required code necessary to make use of the generated hardware. In this way, embedded programmers can offload specific algorithms from the processor to dedicated hardware without knowing anything about the design of the underlying hardware.

Harnessing the full potential of FPGAs
In order to harness the full opportunities offered by programmable devices such as FPGAs, Altium believes designers need a system which raises the abstraction level of the development process to a point where core elements of the design can be easily changed using familiar design techniques and processes. Altium Designer unifies the entire electronic product development process by bringing together hardware, software and programmable hardware. The combination of a unified development environment and the ready availability of cost-effective large-scale FPGAs sets the scene for embedded developers to embrace and exploit the potential offered by programmable devices. With the right development environment, the large reconfigurable design space offered by current FPGAs enables a new approach to be taken to embedded design and allows designers to revolutionize the way electronic products are created, similar to the way the introduction of microprocessors themselves changed the face of electronics several decades ago.

About the author:
Rob Irwin is Product Marketing Manager at Altium Limited. He has a Bachelor of Engineering (Electrical) degree from the University of Sydney, Australia. Mr Irwin can be reached at: rob.irwin@altium.com.au