Employing the USE Metric for New Design Languages

CEO San Jose, CA

As design teams take advantage of new semiconductor manufacturing technologies to produce increasingly complex devices, the pressure to reduce design cycles and iterations is intense.

The most time is spent doing functional design and verification. With the arrival of deep submicron process technologies which enable complete systems to be squeezed onto a single integrated circuit (IC), newer and trickier design problems have emerged. In an effort to solve them, diverse software and unlikely techniques have been introduced which, when combined, have resulted in confusing and problematic design flows.

The most recent attempt to address these system-on-chip (SoC) design problems is the unveiling of new design language proposals. Many recommend tailoring an existing software programming language to the needs of the SoC designer. But tailoring an existing language created to meet a different set of needs is impractical, because design flow problems may not be apparent until the language is applied in a real-world system design environment.

It's worth analyzing what a design language should do to meet SoC challenges. A new language must Unify the complete SoC design flow, Speed up the design process, and allow Evolution from older methodologies. The USE Metric is essential for new SoC methodologies.

The first requirement must be the Unification of the design flow. An existing problem is the multitude of software, languages, and techniques—each solving a specific design problem—that are layered on top of existing design flows. The design flow is hard to use and learn, suffers from software performance problems, and is impossible to maintain.

A new language must incorporate needs of the entire SoC design flow—architectural specification, system partitioning and performance analysis, test specification, software planning, hardware implementation, software design, and functional test application. A single language and software flow that handles this requirement will benefit the entire system design team by providing a common communication mechanism, simplifying the varied activities in the design flow, and eliminating interface bottlenecks.

The second requirement is to improve design Speed. A new language can and should dramatically shrink design cycle times. It can and should leverage greater design abstraction, utilize efficient constructs to aid coding and debug power, and eliminate slow interfaces by providing a single source. It can also enable new technologies that now include model checking and behavioral synthesis.

Accelerating the design cycle is a primary objective of a new language. Designers must be able to start using it quickly, build and debug components efficiently, and utilize up-to-date design techniques.

The language should offer an Evolutionary path from existing methodologies to the new language. No design team can take time to learn a new methodology. Designers need the ability to use their current modeling styles and techniques and, over time, bring in new constructs. A new language must evolve from current techniques.

Many of the new design language proposals, which include the use of software programming languages like C, do not meet the USE Metric. If the project team is forced to use C in the early stages of design, and then to switch to a hardware description language (HDL) for later implementation work, at some point it is likely that the C models and the HDL models will have to be tested together. This involves interfacing the HDL simulator to the C code, usually through the use of the Programming Language Interface (PLI) included with most of today's HDL simulators. This interface is notoriously slow and can decrease simulation performance by a significant factor.

For hardware software co-design and verification test access, other tools are also linked to the simulator through the same interface, causing an even greater slowdown. If a single language running on a single simulation engine can support all of these needs, the inefficient PLI becomes redundant, because the single simulation engine can support the entire design description, improving performance and productivity dramatically.

Let's take a historical view and apply the USE Metric to the original Verilog HDL. Verilog HDL was used for gate-level and register-transfer level (RTL) circuit descriptions, IC modeling, and test applications. It was fast, enabling high-speed gate-level and RTL simulation, easy synthesis, and fast modeling. It allowed netlists, generated from existing schematic capture software systems, to be simulated with new behavioral models, which was an evolutionary approach to implementation.

Applying the USE Metric, Co-Design Automation, in conjunction with partners, customers, and industry experts—notably, Phil Moorby, the inventor of the Verilog HDL—developed a new design language, SUPERLOG™, to dramatically improve the SoC design flow. SUPERLOG represents an evolutionary step from Verilog HDL and utilizes powerful, C-based constructs for system design and decomposition, while providing an elegant and natural coding style.

SoC design complexities require a new and more creative approach to managing design cycles. A new design language is a necessity to unify components of the design flow, provide the speed required to create complex modules, and enable design reuse with a reasonable adoption overhead.