A View from the Top of the EDA Mountain

The optimal vantage point for surveying a vast landscape is from atop the highest mountain. Similarly, the optimal view of an industry's direction comes from its highest offices. The CEOs of the three largest EDA vendors each offered us his outlook on EDA's near-term role and how his company plans to meet the industry's upcoming challenges. Each view represents a distinct approach to common challenges including increasing electronic-system complexity, decreasing product lifetimes, new design methodologies, the need for increasing silicon IP reuse, and the role played by Internet in future designs. Enjoy the view.

Dr. Aart J. de Geus, Chairman and CEO of Synopsys
Walden C. Rhines, President and CEO, Mentor Graphics
Ray Bingham, President and CEO, Cadence Design Systems

Dr. Aart J. de Geus, Chairman and CEO of Synopsys

Clearly, the three biggest challenges are system-level design, timing and power closure (also called RTL to GDSII), and intellectual property (IP) reuse.

To work well, complex systems-on-a-chip (SoCs) must be designed at a high level of abstraction, with subsystems implemented in hierarchical blocks. System verification will incorporate the requirements of hardware/software co-design and co-verification. Synopsys has a broad range of technologies to address these system-level design issues. With products such as VCS, PrimeTime, PathMill, PowerMill, and Formality, Synopsys already provides its customers with a full suite of system-level verification tools. Our Eagle-i product rounds out our solutions with cutting-edge hardware/software verification technology. We have a round of products coming out soon that will break new ground in the system-level arena.

As a design moves down to physical implementation, timing delays occur. Interconnect delays in deep submicron devices now overshadow gate delays as the dominant factor in the timing budget. Therefore, physical implementation of the device, traditionally done via place and route, is critical to meeting timing budgets. Without new technology, numerous time-consuming iterations between synthesis and layout stand in the way of timing closure. Similar problems occur with power closure, because the interconnects in deep submicron processes are so delicate that they are subject to degradation (electromigration), as well as other problematic side effects.

To overcome these timing- and power-closure challenges, we have fully integrated synthesis, placement, and top-level routing, such that both logical and physical optimization come together into one algorithm. This integration, which we call physical synthesis, eliminates iterations and translates into just a few hours of CPU time for iterations that used to take weeks.

With ChipArchitect, FlexRoute and Physical Compiler, Synopsys has made impressive breakthroughs. And to help guide our customers through the transition to physical synthesis methodologies, Synopsys is increasing the size of its applications consulting force.

Controlling SoC complexity while still meeting tight time-to-market demands also dictates the reuse of IP. We are working to establish systematic IP reuse by providing guidelines to help our customers evaluate available IP and by developing methodologies and tools to help them capture the original designer's intent. Synopsys provides the IP foundation that does not compete with our customers' Star IP. In other words, we provide all the commodity IP building blocks that nobody else particularly wants to do, but still needs.

On the design reuse tool front, Synopsys has acquired Leda, which provides a state-of-the-art, programmable RTL code checker. It will help verify whether design descriptions have been written for reuse.

Meeting the challenges of the coming years through advances in EDA technology will enable the next generation of systems, where enormous functionality can reside on a single SoC. This explosion in compute power will usher in a new era unlike any the world has seen since the European Renaissance. Such powerful technology will enable us to eventually crack such riddles as the human genome and solve other mysteries of the universe. Clearly, there's never been a more exciting time to be part of the electronics industry.

Walden C. Rhines, President and CEO, Mentor Graphics

As the EDA community rushes to offer Web-based products and services, we have to evolve new business models and solve the delivery problems first.

Ask most EDA executives what the challenges are for the next year or two and you get a wide range of answers usually focused on their current products. System-on-a-chip is the default top priority, but it is not the true challenge for the EDA community. Each EDA company is searching for a practical e-commerce business model. Ideally, we need to create minimum disruption to existing business while we perfect our Internet operations. The danger in moving to e-commerce too fast is that current business suffers while trying to launch new Web EDA tools while adding new services.

Emotional Commerce is, perhaps, a better way to explain what is going on in the EDA community. Each player fears being left at the dock as the e-commerce ship sails to rich rewards. This year, we expect to see our EDA competitors try everything on the way to becoming the Amazon.com of EDA. The industry's problems would be much simpler if we could ship the tools via UPS like Amazon. Truthfully, the Internet is not able to handle the enormous amounts of complex data used in the average ASIC design. It's simply not practical. The short-term solution is dedicated lines, fat pipes, etc., not the World Wide Web. But these problems are solvable with time and money.

It is very easy to see Web-hosted tools as a new cash cow, and many of us already offer these products and services. Some consulting services also can be provided via the Web. These two areas offer the most practical and immediate solutions to delivering EDA products and services via the WWW.

Among a few EDA providers there is talk of selling not just Web pay-per-use tools and consulting, but taking the next step into contract manufacturing for PCBs and selling all of the components used in a design. This business model represents a step into component distribution and contract manufacturing; two areas that are not well known to EDA companies, but areas filled with deeply entrenched distributors and OEM component players.

Going into e-commerce and Web-hosting design tools is about all that the industry can digest in the next year or two and maintain profitability. Attempting to start several new types of business at the same time could be flirting with disaster. At Mentor Graphics, we plan to continue to offer Web-based products and services and to add as many new items as we can. We feel that the challenge is to keep focused on the EDA business while we solve the problems of e-delivery.

Ray Bingham, President and CEO, Cadence Design Systems

When we consider the challenges that face EDA over the next two years, the real answer lies with the challenges facing our customers. Increasing design complexity, fierce competitive and time to market pressures, a lack of engineering talent, disaggregation of the electronics marketplace, and the explosion of the Internet all present unique problems for our customers and, in turn, the EDA marketplace. This also presents us with a tremendous opportunity. The opportunity lies in our ability to meet customer challenges, and provide increased value as both and industry and as individual companies.

There is no question that the move to system-on-a-chip and smaller process geometries is a universal challenge for all of us. On one hand, the effect of deep submicron causes us to process increasing amounts of detail at a lower level. At the same time, these extremely complex chips force us to higher levels of abstraction, discarding as much detail as possible. The challenge for EDA is to increase the amount of automation between the highly abstracted system level and the very detailed implementation level. The increased difficulty of design is also leading some customers to outsource their designs in order to focus on core competencies.

Customers are demanding more focus on reusable intellectual property and integrated platform-based design. The move to SoC also increases the need for designs that mix digital and analog/mixed signal functionality. This is a challenge for customers, and will result in the need for a true cultural change. This change is analogous to the arrival of the ASIC in the 1980s, and in turn presents a challenge for the EDA industry to better partner with our customers to help ease the transition.

Cadence is addressing all of these challenges by providing the broadest offering of EDA technology solutions, with leadership in key areas that are critical to our customer's success. We can assist customers with their entire electronic product design—whether it's a block of intellectual property, a chip, a board, or an entire system. Only Cadence can provide a unified, front-to-back solution in the synthesis place-and-route market. In addition, Cadence's design services organization offers customers the world's largest independent team of design experts.

There is no question that the challenges facing our customers are daunting. However, the entire EDA marketplace is clearly rising to the challenge. Our industry will continue to provide breakthrough technology solutions, and serve as a valued partner to our customers in the years ahead.