Addressing the Verification Bottleneck

The critical bottleneck design teams are struggling with today is not the complexity of designing a chip or system, or the short schedule, but the verification of the design.

Verifying that a design is functionally correct throughout the design flow is a resource hog. One design team estimates that 90 percent of its CPU cycles is spent on simulation. Estimates of verification taking 50-70 percent of manpower resources are common. It only gets worse—verification complexity increases exponentially with design size. Unless the verification bottleneck is solved, the cost of future electronic systems is going to skyrocket.

Solving the problem requires new software tools and/or methodologies, as has happened in the past. For example, when physical design became the bottleneck, automatic place and route tools were developed to replace layout editors. And when design entry was the issue, synthesis tools were developed to enable more gates per designer. Yet, verification has remained a manual task. This is okay for designs with several thousand gates, but manual verification is extremely limited for today's complex, multi-million-gate designs, which are too big and complex for a simulator to check completely in a reasonable amount of time.

Companies are struggling to solve this problem and are pouring billions of dollars into manpower and technical solutions to fix it. In addition, systems on chips (SoCs) bring their own verification problems into the mix. Some of the issues engineers face with SoCs involve the integration and verification of externally developed intellectual property (IP) and interactions between the hardware and its embedded software. As more and more designs include externally developed IP, how will companies integrate and verify these blocks as part of their complete system? And, as more systems-on-chip designs include processors, how will companies address the complex interdependencies between the hardware and embedded software? It is clear that verification will continue to be a serious problem, and a rethinking of verification methods is needed.

Engineering teams must move to new verification methodologies to stay competitive. Missing a market window because of an unforeseen bug in the silicon can be disastrous. Imagine a personal computer maker having to re-spin silicon and delaying shipment of its PCs because a critical bug wasn't found until late in the design cycle.

Incomplete or inadequate verification is the reason why designs fail and products are forced to miss their market windows. But it doesn't have to be that way. Complex chips, systems, and SoC designs are forcing us to rethink our approach to verification. We are being forced to update and enhance our environments.

Solving this bottleneck includes moving verification earlier in the design flow, to automate what were once manual tasks while disturbing the current flow as little as possible.

It's worthwhile to define and discuss verification in general. A good working definition of verification is "proving a design does what you want it to do." Specifically, engineers write tests against the design and check to see how it reacts to those tests. But with the complexity of today's designs, how do engineers know that the design is completely tested, that all the bugs are found? How do they know that they have tested every possible use of the chip? A common method is to continue to manually write new tests and run simulation until the engineer stops finding bugs, but this process is quickly becoming an impossibility.

A better method is to automate the verification process. Automatically generating functional tests, data, temporal checking, and functional coverage analysis helps engineers finds bugs they haven't thought of—bugs often caused by ambiguities in the specification and/or unanticipated usage by the target system. And adequate coverage metrics quickly point out which parts of the design have yet to be tested. These metrics are important in that they provide a view of the verification progress and make verification more efficient.

Verification has become the most critical bottleneck in electronic design. It must be addressed immediately, or the cost of future electronic systems is going to skyrocket. This can only be achieved by automating the verification process. Automation will allow more complete testing of designs, thereby create higher quality products, and it can accomplish this faster than any manual process in use today.