CICC—25 Years and Counting

Sporting a new time period (September), a return to a familiar location (Silicon Valley), and some new technical sessions, the Custom Integrated Circuits Conference is celebrating its 25th anniversary this year. CICC takes place from September 21-24, 2003 and promises to carry on the conference's theme of "innovation, education, and communication." CICC's shift from its traditional May time slot into the fall now gives both attendees and presenters a more balanced lineup of IEEE-sponsored conferences covering IC development—ISSCC in February, the VLSI Symposia in June and, now, CICC in September.

CICC offers a rich lineup of educational short courses, technical sessions, technical and business panels, and exhibits. As the premier IC design and development conference, CICC has something for everyone involved with chip design, EDA tools, IC-enabled system development, and semiconductor process technology.

Starting off the conference are Sunday's four educational short courses. A great opportunity to enhance your technical knowledge on specific subjects, the full-day courses are taught by leading experts in industry and academia, and target the practicing chip designer. This year's educational-session agenda covers four key areas: Advanced RF, Advanced Data Converters, High-Performance and Low-Voltage Design, and SoC/Mixed-Signal/RF Design, Verification and Test.

The conference's 27 technical sessions comprise close to 150 papers, selected from the more than 380 papers submitted to CICC. Highlighted by several excellent invited and tutorial papers, the technical sessions cover a wide range of chip-related topics including Wireless and Wired Communications, Analog, Custom and Low-Power Circuits, SoC/IP, Simulation and Modeling, Signal and Data Processing, Embedded Memories, Programmable Devices, Fabrication, and Test and Reliability. New this year are two Emerging Technologies sessions featuring several interesting invited papers on biotechnology, nano-technology, and other leading-edge subjects.

Bob Lucky, author of the IEEE Spectrum Magazine's "Reflections" column, will present the Monday keynote address. Dr. Lucky will discuss "Technology in the Midst of the Telecom Turmoil," which he describes as "a survey of the current landscape from the viewpoint of a technologist who hopes to see a new world emerge in which bandwidth is plentiful and cheap, access is mobile and ubiquitous, information is freely exchanged, and research is well supported." The Tuesday conference luncheon carries on a tradition of speaker and subject that are informative and entertaining. This year's lunch will feature Dr. Tsugio Makimoto, Corporate Advisory at Sony, who will discuss critical roles in robotics played by chip technology as well as robotic chip designs being a "technology driver in the coming decades."

CICC's Tuesday evening panels, always a welcome break from the all-day technical sessions, give you a chance to absorb experts' views on varying business and technology topics and to "add your two cents." This year's panels are an eclectic mix of topics:

• Technology: Falling Short of Product Developer Needs?
  
  
• Outsourcing! From Fabrication to Packaging, and now Design—will the U.S. Semiconductor industry survive overseas outsourcing?
  
  
• Are Analog Device Models Really that Bad or are They Just a Convenient Excuse?

In a 'first' for an IEEE-sponsored conference, the "Technology: Falling Short" panel will choose one of the conference attendees to sit on the panel.

Communications

Design and Development of the First Single-Chip Full-Duplex OC48 Traffic Manager and ATM SAR SoC
This work describes the architecture, design results, and design methodology for a high-speed digital communications chip comprising approximately 78 million transistors and supporting a 5-Gbps throughput for 1M simultaneous SAR flows. The paper discusses design hierarchy, functional design via verification acceleration, floorplan and synthesis optimization, and clock architecture, along with timing and electrical design.

A 10-Gb/s CMOS Clock and Data Recovery Circuit with an Analog Phase Interpolator
The authors describe a novel 10-Gbps clock and data recovery (CDR) circuit targeted for multi-channel communication chips. Fabricated in a 0.11um CMOS process, the CDR circuit passes the SONET jitter tolerance test with a PRBS of 2^23-1. Power consumption is 220 mW with a 1.5V supply.

Modeling and Analysis of High-Speed Links
Providing an excellent analysis of noise impairments such as voltage and clock jitter in high-speed links, the authors show that the correlation between the various colored noise sources in these systems is much more important than their total power. This result has significant implications for the type of system architecture that such chips can employ and for the different techniques designers can use, such as equalization and multi-level signaling, for overcoming these system impairments.

RF Design

MEMS for Telecommunications: Devices and Reliability
This tutorial paper provides a comprehensive review of various RF and optical MEMS devices for telecommunication applications and their related reliability issues, including the vast freedom and flexibility in MEMS design and fabrication. Topics the author covers include various IC-like surface micromachining and non-IC-like bulk micromachining fabrication techniques, along with different RF MEMS devices such as RF switches, tunable capacitors, hi-Q inductors, and bulk acoustic-wave filters. Also included are optical MEMS devices such as optical cross-connect switches, dynamic gain equalizers, and optical add-drop multiplexers. The author also discusses typical MEMS reliability issues including ESD, frictional wear, material fatigue, and creep.

Advances in RF Packaging Technologies for Next-Generation Wireless Communications
This RF packaging tutorial covers many issues critical to circuit designers, along with concrete examples that summarize key developments and trends. Particular attention is given to plastic, low-temperature co-fired ceramic (LTCC), flip-chip, and system-in-package (SiP) implementations for wireless applications.

Surface-Mounted RF IC Technology Demonstrated with a 10 GHz LC Oscillator with Copper Coils
Through a substrate-to-glass transfer technique using a surface mounting process, the authors show that by eliminating the need for bonding wires and taking advantage of the low dielectric constant of the glass substrate, the new method reduces parasitic inductance and capacitance. This technique supports the development of a high-performance, low-power 10 GHz LC oscillator with a copper inductor.

DSP

Trends and Challenges for Wireless Embedded DSPs
This tutorial discusses the emerging SoC and circuit-design techniques applicable to DSPs for handheld devices, including the power vs. scaling tradeoff inherent in this cost-sensitive market. Key topics include analysis of architecture selection, low-power modes, leakage management, low-power clocking techniques, and low-power memory design.

Programmable Architectures

Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)
Proposing a device somewhere between a traditional gate array and an FPGA, the via-programmed gate-array has lower mask cost than an ASIC, but smaller silicon area and higher performance than an FPGA. The authors determine that a good logic block for this class of devices contains a look-up table, basic NAND gates, and a register. The via-programmed gate array can achieve speeds comparable to a standard-cell ASIC with 2x-3x area penalties, making it much denser than a typical FPGA.

Emerging Technologies

A Retinal Prosthesis Device Based on an 80x40 Hybrid Microelectronic-Microwire Glass Array
The authors describe the development of a neural stimulating array that may be used as a retinal prosthesis device. The 80x40-cell array uses a glass matrix comprising several hundred thousand microwires to interface to a curved retinal surface. Topics this invited paper covers include device architecture and development along with biocompatibility issues. The test device enables human demonstration of a massively parallel interface between retinal tissue and the microelectronic array.

For more information on CICC, including details on registration visit www.ieee-cicc.org.

Jim Lipman is a consultant providing marketing, writing, and other electronics industry services, specializing in EDA tools and ASIC/SoC design methodologies. His job experience includes chip-design R&D, marketing, marcom, technical editing, and on-line publishing of technical content for engineers.