Designs in every industry segment are built around standard interfaces; you probably can't find a complex chip that does not have some sort of standard interface such as PCI, PCI Express, DDR-SDRAM, USB, HDMI, or Advanced Switching.
Unfortunately for design and verification teams, these standards are all described in documents, many in the 500+ page range, all containing the unavoidable ambiguities subject to human interpretation. To make things even more complex, most implementations of these interfaces are different. In the case of PCI Express, the standard allows for an extremely wide range of device types, features, and functionality, and few chip designs are implementing 100% of the features defined in the specification. Verifying these interfaces is becoming an increasingly significant challenge for chip designers.
Enter the need for interface verification.
What is Interface Verification
The two key elements to interface verification are verifying compliance with the specification, and verifying interoperability with other compliant devices. Compliance verification is largely defined as ensuring that a design adheres to the features and functionality defined in the specification from the standards bodies. The ultimate goal is to ensure that designs can interoperate, or communicate, with other devices in the end system using the interface standard. However, with the freedom to implement various subsets of the functionality defined by a particular protocol specification comes the added risk of incompatibility between compliant devices. Too many companies have learned the hard way that compliance does not necessarily guarantee interoperability.
Figure 1: Languages such as SystemC and SystemVerilog are the right solutions for "inside the chip" and domain expertise encapsulated as IP/verification IP are the right solution for standard interfaces at the "edges of the chip" |
Elements of the Solution
Verification intellectual property (IP) is rapidly emerging as a necessary element of the functional verification solution, especially for complex chip interfaces. Verification IP vendors are able to leverage specific domain knowledge for these interfaces along with verification expertise to provide significant value to chip designers.
And, verification IP is becoming much more than a bus functional model (BFM) or passive checkers designed to monitor a set of assertions at the interface. Commercial verification IP solutions provide the ability to completely verify the interface for compliance and interoperability, and can be leveraged for system-level verification of the overall design.
Robust BFM
A BFM encapsulates the complete features and functionality of the specification, with the ability to initiate and respond to interface traffic. The BFM element must also include the ability to inject erroneous transactions to ensure proper error recovery from the design. Finally, the BFM must provide the flexibility to model all possible configurations of compliant devices. Development of a high-quality BFM requires significant domain expertise and understanding of the interface standard.
Assertion Library
A library of assertions must be tightly integrated with the BFM. Assertions dynamically monitor device behavior against the protocol rules defined in the specification. For a particular protocol, these libraries typically contain thousands of assertions, which must be extracted from the standard specification.
Compliance Suites
Compliance suites are generally defined as a set of tests targeted to exercise specific functionality and corner cases in the specification, including compliance checklist items provided by the standards organizations. Comprehensive suites typically contain several thousand tests to exercise the design. Ideally, the compliance suite is integrated to the BFM such that the appropriate tests can be automatically tailored to the various device configurations in the system.
Test Sequences and Coverage Metrics
Test sequences are building blocks used to generate specific traffic patterns for functional verification. Together with a strong coverage model, this enables rapid generation of application-specific traffic for system-level verification above and beyond compliance and interoperability testing. Again, the test sequence library and coverage mechanism must be tightly integrated with the BFM to ensure context-relevant data generation.
Debug Solutions
There is a significant industry trend in new interface protocols, moving from parallel interconnects, to high-speed serial interconnects. This poses an additional challenge for verification engineers during debug, where the analysis of pin-level activity, useful for parallel busses, is being replaced by transaction-level analysis for serial interfaces. The verification IP solution must be capable of supporting transaction level debug and analysis of data and transactions at various layers of the protocol.
EDA Integration and Portability
Obviously, all elements of the verification IP must be easily integrated into an existing verification environment and methodology. Interface verification solutions have an additional requirement of being highly portable to support easy deployment into all commercial verification tools and languages. This requirement is critical since the verification IP often becomes the central, and shared, element of interoperability verification involving third-party designs. In some sense, the highly portable verification IP serves as the "golden model" used across the industry to ensure quality and interoperability.
Conclusion
Functional verification is a looming challenge for chip designers. Standard interfaces are a natural target for dramatic improvements in verification productivity. The availability of commercial verification IP for standard interfaces is now enabling chip designers to slash a significant percentage of the overall verification cost, and offers an effective mechanism for ensuring chip-to-chip interoperability. The overriding criterion for choosing a verification IP solution is domain expertise. Commercially viable solutions will combine electronic design automation (EDA) expertise with an expert-level understanding of interface standards to provide a comprehensive, high-quality solution.
About the Author
David Lin joined Denali in July 1997 and is currently VP of Applications Engineering. His team's mission is to ensure customer satisfaction through the successful adoption of Denali's technology into customers' environments. He is also responsible for developing and enhancing key memory vendor partnerships. Preceding Denali, Mr. Lin held senior engineering positions at Synopsys and Mitsubishi Electric and had also served on the IEEE 1076.4 VITAL standards definition committee. He holds a BS in Computer Engineering from Princeton University. His email address is
davidlin@denali.com.
