Top Three Considerations Regarding Interface Development

When semiconductor companies plan their chip development, their focus tends to center on the area where they add the most value, namely the core. Regrettably, I/O development is often taken for granted and/or pushed to the end of the development cycle. In fact, disregard for the importance of I/O development can jeopardize the success of the chip. The most advanced core is rendered useless if the data cannot get on and off the chip at optimal frequency and throughput levels. A well-thought-out plan for I/O development and integration is key to producing a successful chip.

Among the key factors for successful in-house design of interfaces are the requisite internal resources (tools and staff), and the time to develop and adequately test the I/Os. Required tools include layout, verification, place and route, extraction, logic and synthesis as well as some form of signal integrity and timing (SIT) analysis software. Often companies will have some of these tools, but not all, which can jeopardize successful interface rollout. Either an investment in tools or outsourcing of portions of the design is then required to complete the interface deployment.

In addition, chip developers must have available design capacity including an engineering staff with both I/O development and SIT experience. None of these are a given, especially when time-to-market pressure, including investor and competitive demands, is brought to bear. Under these circumstances, development efforts tend to focus on the core. By the time engineering tackles interfaces, significant decisions may have been made—examples include packaging and pad pitch—that can adversely impact the ability to successfully develop interfaces that can achieve the target operational goals. An early decision to purchase third-party IP can help to avoid this stumbling block.

Another factor impeding successful implementation of generic I/O IP is the complexity of the system into which the I/Os are being deployed. A variety of system elements can affect the performance of the I/O drivers, including PC board, package, vias, connectors and number/type of devices. Generic, standards-based I/Os do not take these elements into account, and redesigning these pads is both a significant challenge and added expense. Furthermore, it adds risk and time to the design process, making purchase of this generic I/O IP nearly as problematic as developing interfaces from the ground up. Once again, companies need to consider whether they have the time, talent and experience on-hand to redesign this generic I/O IP.

Especially troublesome is that while SIT was once a staple of any engineering study, it has become more of a lost art these days. While larger companies will have SIT experts on staff, this is often not the case with smaller outfits. Detailed SIT analysis is critical for successful rollout of high-performance I/Os.

Ron Nikel is Co-Founder and Chief Technology Officer of TriCN (founded in 1997). A 1992 graduate from Cornell University with a M. Eng. Electrical Engineering, Ron Nikel worked at Digital Equipment Corporation from 1987-1991, where he specialized in circuit design and signal integrity on the VAX 10000 and DEC 7000 servers. In 1993, Ron joined Silicon Graphics as a Circuit Interconnect Technologist for the Origin 2000 program where he developed the Craylink technology as well as the copper 500Mb/s and the 1Gb/s optical interface for HIPPI-6400-PH standard.

This article was published in Electronic News, 11/25/2002. Republished in TechOnLine with permission from Reed Electronics.

For more information about I/O development, visit TriCN's Web site.