Hands-on: Get started in analog IC design and fab (Part 2 of 3)

Instead, it describes how an experienced engineer undertook to teach himself analog IC design, including his planning, the tools, the sequence of events, and the actual IC fabrication process. Whether you are thinking about learning analog IC design yourself, or just want to see how you can use available resources as part of self-paced continuing education regardless of your engineering career stage, you'll find it of interest and with actionable lessons and take-away information you can use.)

We are pleased to present this feature, in three parts:

• Part 1: Goals, sources, curriculum, and "exams", click here
• Part 2: The thesis project and MOSIS, below
• Part 3: Free tools, Tanner tools, and finishing, will appear soon

The thesis project and the MOSIS secret
As mentioned before, the thesis project is the centerpiece and the most important part of this microelectronic training program. It will teach you a lot and it is the most visible part to potential employers. Most of us never imagined that it might be possible and affordable to just haul off and create your very own chip. Well, I'm here to tell you that the secret is out: Any serious IC design engineer can create a chip layout and have it fabricated at a very affordable price, through multiproject wafer organizations such as MOSIS, Figure 3.

They integrate large numbers of different projects on a single wafer and contract with various foundries to produce the wafers. There are many processes to choose from, at different prices. While you only end up with a small number of samples of your part, the cost of doing the fabrication is orders of magnitude less than it would be if you tried to contract with a foundry to run your design alone. The fabrication fee for my project in a 5V, 1.5 μm CMOS process was about $1300. Unfortunately, this particular process has been discontinued.

Bear in mind, though, that the primary purpose of MOSIS is to provide free or low-cost fabrication services to universities. It is run by the University of Southern California. As you can imagine, there is no way that they could function if they had to support all of the thousands of students out there, directly. That is why they only work through a professorial contact at each institution. Students are not allowed to contact them directly.

They do provide the services for commercial customers, as a way of paying the bills for their academic work. Home schoolers don't qualify as academic institutions, so we must apply for accounts as commercial entities. My account is under the legacy proprietorship business I have, called Tesoft. They were kind enough to accept me, even though I look a whole lot more like the students they avoid instead of the professors they support.

In return, I have done my very best to minimize the burden on their technical support people. You should too. Make sure that you read every FAQ and explanatory document on their website very carefully before sending questions to their support. You can find lots of information about working with MOSIS on Baker's website and others. Also try the MOSIS_Users_Group at yahoo.com. Do not try to run a chip until you have fully educated yourself about doing chip design, both electrically and physically. Do everything you can to get your question answered on the Web before pestering MOSIS. Remember that this is a service primarily for accredited universities and you are a guest.

Okay, let's say that you have finished your initial courses and are ready to start defining a thesis project. The first step in narrowing down the available options is to choose a process. First of all, I haven't seen much evidence of multiproject bipolar processes, though BiCMOS processes exist. This means that CMOS of some kind is pretty much the only game in town.

Probably the most important consideration is the cost of fabricating the chip. For more advanced processes, fees of $20K and more are not unusual. You generally pay more as the feature size goes down and special features are added (e.g. bipolar devices). At MOSIS, the cheapest run I could find was the one I used: 1.5 μm CMOS, at about $1300, including five packaged parts.

As mentioned above, sadly, this process has had its last run. The next most affordable process at MOSIS is 0.5 μm CMOS at $4600, and includes up to 40 die. Add roughly $35 per part for the number you want packaged. Of course, prices are subject to change. I'm just trying to give you a feel for what ballpark this is in.

The costs that I am discussing here are for the minimum billable chip area. For the 0.5 μm process, that is 5 mm² which should be sufficient for a student analog project. My opamp chip was 3.2 mm², including two copies of the amplifier and 28-bond pads. (The pad area does count and it's big!)

There are other multiproject wafer services. For example, CMP, Figure 4, offers a 0.35 μm CMOS process for about $2500 at present currency rates. That includes 25 die, with five of them packaged, and a die-size up to 3mm².

It's in France, but they have lots of U.S. customers, so home-schooled student projects are still affordable. Since analog characteristics of CMOS transistors tend to get worse as feature size is reduced, there is little incentive to choose a more expensive process with smaller features. The bottom line then, is that you will probably want to go with the cheapest CMOS process you can find.

The next step is to decide what you would like to build. I found that this became a tradeoff between interesting and doable. Here is where profs and regular schools have an advantage. The profs would have a good feel for what students can reasonably accomplish in a semester and they can organize teams to split up the work. It is unlikely that a home-schooled student is going to find a partner on a student chip project.

As far as estimating completion time: first of all, I will tell you that there is no way that you can do it in a quarter. The criteria that you have used in the past to estimate project schedules don't apply well because, every step of the way, you will be learning something that is new and different from the board-level designs with which you may be familiar.

One thing that makes it so different is the fact that everything must be predicted. Breadboards can't help because you don't have the devices and there would be too much stray capacitance anyway. It becomes necessary to spend a great deal of time with modeling and simulation. Some aspects that you would think would be built into the models, aren't.

For example, the drain-to-body capacitance of a MOSFET is important in the AC performance of an opamp. But the amount of capacitance depends on the area of the drain, which is affected by how it is laid out. It is not a simple function of the width of the device. Larger devices can use interdigitated layouts which utilize both sides of the drain, reducing capacitance for a given width. I did sample layouts and developed approximations to estimate source and drain areas. The formulae became part of the Spice model file, which handled the estimates transparently.

So you end-up learning lots of things about MOSFET modeling and semiconductor technology along the way. It's all interesting and fun but it takes lots of time. One thing that increases the time is that you don't have anyone you can ask all of those zillions of simple questions that someone who has done this before would already know.

You might think that there would be user forums. There are, but this is a small arena. The chances are small that someone out there is familiar with your particular process, knows the answer and is monitoring the forum. The multiproject wafer people are not setup to handle newbie questions. That's why they work with only the profs.

When I tried to contact the process vendor, the messages went unanswered. You can imagine that supporting all the newbie users of a multiproject wafer run is not high on their priority list. Finally, due to strict confidentiality agreements, there can be little posted information from people who have used the process. They also have to be careful what info they post on the forums. I did find the occasional thesis or student paper which helped, though.

This situation is not all bad. With enough effort and research, you can answer all questions or work around them. In many ways, that experience enhances the value of the education program. You learn a lot more than if you simply had a prof to ask questions of. You become more capable of solving your own problems.

All this boils down to the simple advice that you should choose a project that you think is relatively easy. It won't be. Remember that it is just a student project, not the World's next great chip. There is a tendency to want to do something which could impress people. Resist that urge. No one will be impressed with a chip that doesn't work.

I chose to do a plain "commercial" op amp. By commercial, I mean that it is designed for use at the PC-board level as opposed to embedded, on-chip applications. The specs were mostly vanilla, as listed in Table 3:

Table 3
(Click on image to enlarge)

Of course, as engineers, we are taught to try to optimize our design choices. The design of an analog IC becomes a huge optimization problem, with the stated specs (and many unstated ones) as variables. In the end, it all gets optimized to fit in a given chip area. That can be a challenging task, even with relatively simple products.

For example, I realized that the input noise level would be a function of how large the input devices and their current-source loads would be. To optimize that, I did a spreadsheet which calculated equivalent input noise, based on the areas of the devices. Then I had to estimate the areas of the output devices and other major parts of the design. Working with the area available to the input and load devices, I was able to optimize those for minimum noise.

All of that made for quite a challenge in this vanilla op amp. Admittedly, it was intensified by a desire to achieve exceptional noise performance, which is somewhat unusual in CMOS op amps.

By the way, there was no noise data available for the process. I had to research similar processes to find the data and that took a lot of time. In summary, be very conservative with how big a project you choose. Remember that as part of the design process, you will have to be able to prove that every aspect will work and you may not have a second chance at fabrication. The schematic of my opamp is shown in Figure 5.

Figure 5: Schematic of the op amp of the final project
(Click on image to enlarge)

(End of Part 2)

About the author
Steve Lafferty holds an MSEE degree and has been working in electronic design for over 30-years. He was previously a principal engineer at Wegener Communications. Having just finished a two-year educational program in CMOS analog design, he is now available for employment in that or a similar field. He can be reached at slafferty@bellsouth.net, 770-664-6192.