NPUs and FPGAs: on different planes?

When the key communication designs to win were those involving core gigabit switches or metropolitan service routers, the question occupying the members of the Network Processing Forum was what it might take to have ASICs replaced by standardized network processors. Some were predicting the death of the ASIC; others were wondering whether the market for network-processing units would ever be big enough to sustain more than three or four players.

True ASICs, with millions of gates, long lead times and high nonreturn on engineering costs, have little place in networking outside massive routers like the Cisco CRS-1. IBM probably can sustain a business in its high-end Blue Logic ASIC effort, but there's not a lot of communication business out there for LSI Logic or the Japan-based gate array players.

The interesting arena at the edge, however, involves standard NPUs, fixed-block FPGAs and soft-core FPGAs. The issue is rarely a head-to-head battle, but instead involves carefully delineating areas of the control plane and data plane where different architectural types should predominate.

Best of Show

For a good example of what I'm talking about, check out Tel Aviv-based Crescendo Networks, which won Best of Show at the May NetWorld+Interop show. Crescendo calls its system an enterprise application front end, or AFE, intended to replace a first-generation load balancer with a special architecture for handling 1-Gbit/second data center traffic to server network interface cards, particularly in efficient transport control protocol offloads and remote direct-memory-access calls.

Crescendo originally intended to offer a simple interconnect fabric based on Infiniband but saw a market for taking on such data center tasks as Secure Sockets

Layer offloads, compression and caching. That meant plenty of extra hardware assists and heavy lifting on the silicon end.

"You couldn't use FPGAs alone for this mix of functions," said Steve Elston, chief of U.S. operations and marketing at Crescendo. "We needed a standard network processor for its programmability and flexibility, the Altera Nios II processor for the soft-core functionality and Stratix FPGAs for the more advanced functions."

Buddy systems The networking world long ago outgrew the model wherein FPGAs are used only for prototyping, after which designs are converted to traditional ASICs for high volume. In networking, volumes are never high enough to warrant designing out the FPGA. Now, the complexity of compact, efficient edge boxes showcases the fact that NPUs and FPGAs do not have to compete in a race for sockets. In most designs, they can be the best of friends.

Loring Wirbel is Communications Editorial Director for EE Times and its network publications.