SOI sharpens the leading edge as silicon scales to 90 nanometers

Over the last 40 years, the electronics industry, a major economic contender weighing in at the $1 trillion range, has relied on a single raw material — silicon — as the foundation for all electronics-based products. Now considered a commodity, thanks in part to its global pervasiveness, silicon has been the key ingredient used in the manufacture of semiconductors that power today's advanced electronics devices.

Major innovative breakthroughs in the semiconductor industry, however, are no longer expected to come solely from silicon material. Silicon wafers are highly perfect and this is critically important for achieving high device yield. The introduction of 300-mm diameter wafers reduces the cost per chip, while the new generation of equipment needed to implement the larger wafers further improves their quality.

But a more radical change may be needed in the material structure, processing method, or device design in order to enhance the circuit performance. Today, silicon wafer manufacturers are investing only 4 percent of their revenue in R&D, as engineers constantly strive to make silicon products both better and cheaper.

Innovation often comes where it is unexpected. After several years of considering the impact silicon may have on the intrinsic performance of devices, the industry's race to smaller geometries has brought silicon back to the center of today's performance-improvement debate. Specifically, there are several contributions to bottlenecks in this particular arena.

The interconnect revolution was the first step toward creating an opportunity for silicon innovation. The introduction of copper and then low-k dielectric interconnects became the clear enabler for the industry to keep pace with the mandates set forth by Moore's Law. With the push for increasingly smaller devices, semiconductor manufacturers faced two major challenges: reducing power consumption and boosting device performance — all while accommodating the scaling demanded by the most recent International Technology Roadmap for Semiconductors (ITRS). The need to drastically reduce power consumption has been fueled by the mobile revolution, where power provided by batteries is at a premium. There are also major heat-dissipation challenges associated with the high-speed circuits contained in high-performance stationary and mobile systems. At the same time, multimedia and MIPS-driven applications require new technological solutions, since scaling is not enough to guarantee a doubling in device performance every 18 to 24 months — to keep up with the demands of Moore's Law .

By offering an opportunity to deliver higher speed, while also lowering power consumption, SOI was created to combat these bottlenecks — head-on. Conceptually, SOI has been in existence for a long time. In 1945, one of the first patents on the MOS transistor structure earmarked the advantages of having an oxide layer beneath a transistor structure. But it wasn't until the 1990s that the industrial manufacturing capabilities to create high-quality SOI wafers were in place.

Today, SOI is needed to extend the life of traditional silicon technology. In addition to boosting speed and reducing power consumption, the use of an isolated thin film of silicon solves some of the scaling difficulties involved with semiconductor functionality. The first few process steps performed on a silicon wafer in standard CMOS technologies are to establish isolation between the transistors. These processes require high-energy implanters and lithography steppers, the complexity and cost of which increase when the geometry of the transistors goes down to the 90nm and below geometries. By including isolation in the wafer at the raw-material level, many of these process steps are removed, resulting in cost savings and offering a degree of isolation impossible to reach on standard silicon by enabling more transistors per unit area.

In all, these advantages make the shift to thin SOI structures an attractive solution both in performance and cost. The next decade will see SOI becoming the industry standard, concurrent with the shift to 300-mm-diameter wafers — at this wafer size SOI technology is expected to dominate.

Challenges ahead

Good timing has contributed to the industry's transition to SOI, which coincides with a very important milestone in semiconductor history. As the 300-mm generation of silicon wafers begins to find its way to large-volume production after being in the starting blocks for at least five years, the development of technologies below 100nm (90nm, 65nm, 45nm) requires highly engineered substrates to solve challenges of manufacturing devices at such miniscule geometries.

Soitec's Smart Cut process — which has been applied for high-volume 200-mm SOI wafer production since the introduction of SOI in the mainstream arena for the 180-nm generation — has proven the success and availability of high-quality SOI wafers. The next challenge is addressing 90-nm and below technology nodes, which are facing the transition from partial to fully depleted SOI-CMOS operation, along with chipmakers' shift from 200-mm to 300-mm wafer production

Soitec's Smart Cut roadmap has been defined to address ultra-thin SOI layers for the 65-nm node and below geometries, and focuses on both 200- and 300-mm manufacturing for ultra-thin products with full commonality among process and toolset technology. The timeline indicates production initiation for high-volume products. Source: Soitec

Looking ahead at the SOI-wafer roadmap, several challenges become evident. The top silicon film in the SOI structure has to scale down both for thickness and uniformity, with values approximately 20-nm and 2.5-percent, 6s. These requirements lead to 10... thickness accuracy on a 300mm wafer. Such high uniformity needs to be guaranteed, whatever the spatial wavelength, with a detection level at the angstrom scale of roughness measurement. Currently, thin-film thickness is checked by means of optical methods such as reflectometry and ellipsometry. This gives a measurement of the average thickness on an area of the size of the laser spot used by the instrument — typically, in the range of a few square micrometers.

However, due to the move to fully depleted devices, some of the transistors' electrical parameters are fixed by the top silicon film thickness. This thickness, therefore, needs to be controlled at the nanometer lateral scale. A new concept dubbed 'nano-uniformity' should guarantee uniformity at the transistor level, increasing new metrology tool requirements. Recent Smart Cut developments show that this target can be reached.

The semiconductor industry has grown through relentless innovation. Now, new technology innovation is destined to emerge from applications long considered commodities. Forward-thinking companies and technologists are examining and experimenting with new approaches such as strained silicon and SOI — no doubt the next step on the silicon-evolution scale aimed at tomorrow's high-end electronics products.