A closer look at clock frequency, bus timing, throughput and battery life

A reduction in core clock frequency will reduce the power consumption of a handheld device during the processing of certain tasks, with almost no reduction in performance (see article in this series "Clock Scaling Conserves Energy"). In taking a closer look at the actual numbers, some interesting issues arise.

For example, looking at the table that shows the actual results for battery life and data throughput, the most obvious question is: Why is power consumption lower and battery life longer at 162 MHz than it is 103 MHz? It would seem logical that power consumption would be higher at the higher clock frequency. The reason becomes clear when examining how the software adjusts frequency for the Intel StrongARM CPU on the HP-Compaq iPAQ.

In the StrongARM CPU, a series of register settings are used to set up timing for Flash memory, SDRAM, and PCMCIA peripherals. These register settings are adjusted based on a base clock frequency that is determined by programming a register that controls a phase-locked loop (PLL). The CPU core operates at either the frequency set by the PLL or at twice the frequency. Thus, if the PLL is set at 103 MHz, the CPU core can be programmed to operate at either 103 MHz or 206 MHz. Normally, the core on the iPAQ runs at 206 MHz.

So, in the table, the 103 MHz and 206 MHz entries both use a base PLL value of 103 MHz. In this case, since the external peripheral interfaces are timed at the same rate in both cases, the differences in throughput and battery life are related only to the CPU core frequency change. To achieve the 81 MHz and 162 MHz entries in the table, the same concept is used, but the PLL is programmed to achieve a base frequency of 81 MHz.

The difference in battery life between 103 and 162 MHz is explainable because - for these specific tests - the registers that adjust timing to the peripherals are not adjusted from their default values (based on 103 MHz) when switching the PLL to 81M Hz. As a result, the peripheral timings lengthen. For example, if a PCMCIA timing register setting was twenty clock periods, at 103 MHz, the interval would be 194 nanoseconds, but at 81 MHz, the interval would be lengthened to 247 nanoseconds.

How does this affect power consumption and battery life? With the extended interval at the core clock frequencies based on 81 MHz (both 81 MHz and 162 MHz), the external busses run about 20% slower, resulting in an additional reduction in power consumption. In analyzing the table above, the result is that the slower bus timing (81 MHz) and higher core frequency (162 MHz) has a more significant reducing impact on power consumption than does the faster bus timing (103 MHz) and lower core frequency (103 MHz).

The conclusion to draw is that the external busses have a great impact on power consumption too. As a system designer, you'll have to balance external bus performance with battery life. As with core clock frequency, sometimes faster is better, and sometimes not.

— Andrew Girson, InHand Electronics Inc.