Hardware crucial for mobile DSPs

The challenge for the wireless world is to find a way to deliver needed functionality along with channel bandwidth while consuming the least amount of power. A mobile DSP architecture must have a capable array of functions, which relate to extracting information from the sampled signal, to be able to perform the required applications adequately.

Mobile digital signal processing requires fast and accurate processing. That usually means the user has to be aware of, and automatically manage, the gain throughout the processing. Each sampled word at the input carries the accuracy of the A/D converter; a 14-bit A/D represents as much as 84 dB of signal to noise. After the analog-to-digital conversion, the subsequent digital signal processing must maintain the valuable signal to noise. That requires adequate binary precision throughout the digital processing.

Additionally, the more involved operations, such as butterflies, usually process the same data many times; and since the butterfly operation has digital gain by as much as 1 bit for every time it is used-more for the higher-radix butterflies-the data must be scaled back to the precision of the operation. Scaling can take as much as 6 dB from the sampled signal, thus requiring sufficient bit precision by the digital signal processor.

DSP is at the same crossroads as the microprocessor was back in the early 1980s, and there are many architectures vying for the crown. It will go to whichever architecture scales smoothly up and down the spectrum of emerging applications at the chip, board, unit and system level. Examining application scaling from the system level down, seamless interfacing at all levels involves removing any bottleneck from the free flow of data as it is processed. To achieve smooth processing flow in DSP applications, the system architect is wise to build around the dominant functional structures and the adequate feeding of those structures.

Classically, signal processing has rallied around the concept of convolution for filtering and several other applications. Digital signal processing not only uses convolution but also takes it further thanks to the genius of the Fourier transform and its modern implementation: the fast Fourier transform (FFT). Applications that use the FFT can require logarithmically fewer operations.

Any DSP architecture that properly uses the FFT as its dominant data structure not only enjoys its legendary efficiency but also gets entry into the frequency domain as a windfall. The frequency domain brings new insights and concepts all but impossible in the time domain.

A few of those enabling abilities are:

• concurrently tracking the phase, amplitude and frequency of multiple signals-possibly even thousands of signals-over time;

• dynamically equalizing a communication channel while avoiding the corrupted areas of the spectrum-again, possibly thousands of channels; and

• correlating two-dimensional and three-dimensional images to give "eyes" to the emerging real-time visual world of the Internet and its promised virtual reality.

With chips carrying 100 million or even a billion transistors on the immediate horizon, the implementation of very-high-radix butterfly structures and their supporting functions are possible at the silicon level. To meet the desire for scalability at the silicon, board, unit and system levels, these structures need to be modular and easily cascaded in a step-and-repeat manner. The bottom line for any architecture is its efficient performance of the required applications while preserving the desired information.

It is paramount in mobile DSP applications to minimize power requirements-and it all starts at the silicon level. Every chip dissipates power by the formula P=(C)(V 2)(F), where P is the power, C is the capacitance, V is the voltage and F is the frequency. Examining this formula shows that the dominant term is the voltage; the power dissipation goes up by its square. This explains the chip industry's continual progression to lower and lower voltages to maintain an acceptable chip package size. This lower voltage usually comes from the continued shrinking of chip geometries.

If the selected architecture

can be quickly applied to these smaller and smaller chip geometries, through a step-and-repeat process, the overall system power dissipation will also shrink.

The driving cost of wireless software engineering continues to be a top concern. The military has a motto that essentially says that if you want it to work, have it implemented in hardware. In real-time DSP systems the software requirements are truly demanding. The sampled signal will not wait for slow interrupt responses and bulky operating systems. Any architecture that addresses and minimizes these demands on the software with high-value hardware structures will go a long way toward setting a standardized platform.

Stepping blocks

During microprocessors' most rapid rise, a concept called in-circuit emulation helped the embedded community immensely by placing the microprocessor in the actual target environment, where it could be stimulated by the actual signals it would see once deployed. With a step-and-repeat modular architecture and the quantum leaps in capability of the current hardware-simulation languages such as VHDL, a modern real-time DSP system can in most cases be simulated from end to end by adding the proper number of the step-and-repeat blocks as required by the application.

Application software development is critical with any enabling technology; as problems are solved a library of techniques and routines is built to give the industry insight into many application possibilities. If the DSP architecture is truly scalable, these techniques and routines will mesh into increasingly valuable structures as building blocks for the next emerging application. The winning DSP architecture will facilitate a road map dotted with a long succession of killer applications.

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