Packet processors work with DSPs

With next-generation packet networks becoming the norm, and network operators needing to support higher bandwidth services over wireless infrastructure systems, designers continue to look for ways to drive down costs.

Forklift solutions remain as unrealistic as ever. Network operators wanting to use these new and efficient packet transportation mechanisms must still achieve the best return on investment for their shareholders from the installed base of TDM and ATM equipment.

This requirement is driving the development of multiprotocol systems that bridge the "old" and "new." Designers now have the option of using specialized, high-capacity, application-specific packet processors for VoP (voice-over-packet) and TDMoP (TDM-over-packet) applications, in place of standard DSP and RISC microprocessors.

Packet processors will help drive down the cost of these systems by up to one-third, reducing the number of DSPs and RISC microprocessors that high-capacity TDM-to-IP conversion requires. Using packet processors cuts the need for time-intensive software developments. Expect these processors to play a key role in wireless network elements such as Mobile Switching Center (MSC) and Radio Network Controller (RNC) and the gateway.

DSPs do have an important role to play. They are the ideal choice for algorithmic functions like echo cancellation, compression and DTMF-but not for high-capacity TDM-to-IP conversion.

The required functions for a TDM-to-IP system fall into two basic areas: voice processing and packetization. For voice processing the functions that need to be implemented include echo cancellation, compression, voice activity detection, CNG, silence suppression and DTMF/tone detect/fax relay. Packetization requires RTP/RTCP processing, payload construction, jitter buffer, ATM AAL1, AAL2 or AAL5 and IP/-UDP/Ethernet.

A prime consideration when developing an interface to the packet domain is how to maintain a high level of voice quality while also achieving a cost-effective implementation. The DSP/microprocessor solution does neither of these particularly well. Significant levels of silicon are used, coupled with a nondeterministic level of channel density and latency through the system.

It's no surprise that dedicated packet processors are emerging to take this application area by storm. High-density systems using packet processors will eliminate the use of RISC microprocessors for the packetization function, while also reducing the number of DSPs needed for voice processing.

Using packet processors in wireless applications will yield the following advantages: higher density, including simple scalability to OC3 and beyond; significant increases in price-performance, achieving 25 cents per channel for the conversion process; simplified system design, from memory configuration to application software; very low and predictive latency, an important factor for VoP systems where quality-of-service (QoS) is paramount; and significantly reduced power dissipation and board real-estate requirements.

Predictable delays

Engineers can achieve significant integration by implementing in silicon all the functional elements necessary to perform the packetization process. Flexibility is produced via the Call Control microprocessor, which gives the user complete control over payload size, header construction, jitter buffer size, addressing and network monitoring.

Due to the hardwired nature of packet processors, the latency through these devices is a few hundred microseconds-and this is a predictive latency regardless of traffic volumes. These processors incorporate mechanisms for flow control, which make it possible to treat voice and data traffic appropriately on the packet network, thus facilitating QoS.

Hardwired packet processors also simplify the application software. Once the call is established, construction of the packets is handled completely within hardware. This permits developers to write application code efficiently, by making use of the extensive high-level API and drivers.

Packet processors are also ideally suited to ensuring the timing integrity of the TDM infrastructure across an asynchronous packet domain. Adaptive clocking and primary reference clocking ensure the timing integrity. These techniques are essential when employing circuit emulation for transferring multiple channels of voice traffic over a packet network from an MSC to a gateway, or from a large-scale RNC to an MSC, while maintaining the TDM timing to Stratum 4E/3E levels.

In the future, designers will use packet processors for certain voice-processing work now done by DSPs. For some voice channels, processors can perform VAD, CNG and silence suppression, easing the load on the expensive DSP array.

With the mobile companies leading us from a wireless 'telephony' to a wireless 'communications' future, the strain on the infrastructure will increase, as will competition. But profits need to be made, and packet networks offer a return on investment.

See related chart