Switch-fabric options baffle board designers

Ray Alderman, executive director of VITA (Scottsdale, Ariz.), a sponsor of the meeting, said the aim is to replace the shared-bus standard, PCI, with something far more applicable to today's connected environment. Given data rates in the gigabit-per-second range and clock rates in the gigahertz category, he said, "PCI has just plain run out of steam." Alderman sees "a wide range of switch-fabric alternatives . . . emerging as potential replacement."

Their genesis comes from three basic sources: system-box to box-switch fabrics, board-to-board solutions and chip to chip-level derived alternatives. "They all share a number of basic problems, none of which have sufficiently been addressed: power dissipation, pinout and sufficient real, vs. theoretical, bandwidth," Alderman said. "Each addresses these and other problems from their unique perspectives and as a result do not completely provide the necessary full solution if this market is not to fragment and instead grow."

This week's Focus looks at a number of alternatives through the eyes of engineers who are on the leading edge of next-generation board-level solutions. One fact is clear: The claims and counterclaims of the various specifications pose difficult choices for designers in this new interconnect-rich environment.

The decisions engineers will have to make can be summed up by the experience of one design team at Spectrum Signal Processing Inc.'s Wireless Systems Division (Landover, Md.), which has been designing a software-defined radio (SDR) application. "The wide range of interconnect options certainly gives us a lot of choice," said system architect Lee Pucker, who worked with system engineering manager Frank Van Hooft and development engineer Vivian Ward on the company's recent SDR-based wireless basestations. "And I think the choices — the many, many choices we have now — are much preferable to the situation in past years. Then you had only a few choices and the decision you faced was whether to stick with a standard interconnect and, if the application allowed it, take the hit on performance in favor of cost and time-to-market; modify the standard interconnect and be stuck with a noncompliant implementation; or just develop a completely customized solution that fits the specific requirement in a particular design, adds to the development time, and is not much use elsewhere."

The biggest issue with PCI/PCI-X, he said, is that because it is a shared bus it can easily exhibit nondeterministic latencies. A single card can capture the PCI bus, which sets a limit on system reliability since the bus will be unable to function until the faulty card is removed. The other legacy interconnect they consider was Raceway and Race++. A big advantage of the extended Race++ version, he said, was that the aggregate system data rate can grow, depending on the number of node-to-crossbar and crossbar-to-crossbar links in the system, into the gigabytes-per-second range. But while the crossbars provide some isolation between boards in the system, which can improve system reliability, Raceway typically uses an active backplane architecture consisting of one or more active crossbar devices. For any high-availability system, he said, the failure of a crossbar will often require shutting down the entire system, which limits its usefulness.

The design team looked at several parallel packet-switched topologies such as parallel RapidIO and Hypertransport, which typically support high-link bandwidth with low-protocol overhead, making them very attractive for distributed transceiver architectures. "We also felt that since they have scalable bus widths and clock rates that would allow them to meet both current and future system requirements. But parallel RapidIO and Hypertransport were ruled out, he said, because their limited I/O pins and signal skews become significant considerations when signals are routed across a backplane.

Serial packet-switched technologies, such as switched Ethernet, Serial RapidIO and Infiniband seemed to be the way to go for an overall interconnect topology for their design because they all use a single differential transmit and receive pair to provide the physical layer connection between the end points. More important, Pucker said, they typically support transmission over a longer range, making them ideal not only for board-to-board communications, but also for chassis-to-chassis.

While the team did look at Infiniband, because it uses differential signaling at 2.5 Gbits/second with 1x, 4x, or 12x data signals to provide raw bandwidths of 250 Mbytes/s, 1 Gbyte/s and 3 Gbytes/s, the specification was a bit of overkill for their design, since the 2.5 Gbits/s rate is too fast for most existing backplane connectors. This mean a new connector will be needed to allow these speeds to be used reliably. While it is designed to communicate over fairly long distances, at 2.5 Gbits/s it required too much amount of power for their purposes. "Finally, the complexity of the Infiniband protocol requires significant resources, in logic and software, making it, in general, too cumbersome for use as an embedded fabric for low latency deterministic communications," said Pucker.

Ultimately, the team went for a mixed-bag solution, using a combination of parallel and serial RapidIO, for digitized IF, interboard and interprocessor communications. "But this was primarily because these two technologies share a common, efficient, protocol stack," he said. Gigabit switched Ethernet emerged as a strong contender for payload and control data within the chassis and particularly going outside the chassis. But if Ethernet's speeds prove insufficient, he said, the team is looking at Infiniband, which may be substituted outside the chassis.