Design Article
Not all mezzanine buses are created equal
Larry Smith, Vice President, Robert Perez, General Manager,SBS Technologies Inc. Albuquerque, N.M.
1/17/2002 12:42 PM EST
Over the past year, many mainstream networking and Internet equipment vendors have enthusiastically adopted a mezzanine bus strategy for the sake of its hallmark design flexibility. However, telecommunications equipment vendors have tended to reject mezzanines because of the additional cost they add to a system.
Granted, mezzanines do add somewhat to the cost and complexity of system boards, but they also provide insurance against obsolescence. Those who build their large system boards by locking down all of the SCSI and Ethernet protocols, for example, have limited their flexibility and may find their products rendered obsolete within a year. In contrast, by putting mezzanine slots down on their boards, they can easily upgrade functions as required, extending the useful life of their systems.
The bottom line: Mezzanine boards are an easy way to customize a system using off-the-shelf components, minimizing engineering efforts and the monies that have to go into that, and allowing a quicker time through the development cycle and to market.
All mezzanine buses, however, are not created equal. Each has its particular limitations. The PMC and PC-MIP, for example two standard mezzanine bus architectures are both based on PCI, but all functions do not map equally well to both. One important difference between the two is form factor, with basic PMC boards measuring 75 x 150 mm and basic PC-MIP boards coming in at a much smaller 47 x 90 mm. That means that a PC-MIP board can accommodate fewer components and connectors than a PMC board, but it's possible to place a larger mix of PC-MIP boards on a system carrier board.
Where the PC-MIP mezzanine bus excels is in the ability to mix and match functions on a system board or carrier board. It's so small, in fact, that as many as six mezzanine boards will fit on a typical carrier board: either a 6U Eurocard (CompactPCI or VMEbus) or a full-size desktop PC board. A PMC carrier board, in contrast, can comfortably accommodate only two PMC boards. A 3U carrier can hold only a single PMC board but as many as three PC-MIP boards.
This density issue can have economic effects. According to the PC-MIP draft specification, "Module density is closely associated with overall costs. More modules per carrier board means fewer boards in the host system."
For a head-to-head comparison between PC-MIP and PMC, consider Ethernet, one of the most common mezzanine board functions and a rapidly moving area in which embedded-computer users are demanding higher and higher speeds and more and more channels. For a single 10- or 100-Mbit/second Ethernet channel, there will be essentially no performance difference whether the function resides on a 32-bit, 33-MHz PMC board or on a 32-bit, 33-MHz PC-MIP board. But because of its form factor, PC-MIP presents some real estate problems when the system requires that the Ethernet port be brought out through the front panel.
The difficulty is that the tiny bezel footprint of PC-MIP is too small for conventional RJ-45 connectors. To date, there is only one RJ-45 connector available from one manufacturer that fits within the height envelope of a PC-MIP front panel. This eliminates the flexibility of being able to choose among multiple connector sources. And even with this small connector, it's often a challenge to fit it within the PC-MIP real estate constraints and still be able to achieve EMC compliance.
The difficulty in using PC-MIP for Ethernet arises in systems emphasizing high port count or faster (Gigabit) Ethernet, and many system designers are moving in these directions. Higher port counts are also being used to add flexibility.
It's conceptually possible to have a PC-MIP board with two Ethernet ports in which one port is routed to the front panel and one to the rear. However, real estate on a PC-MIP board is at such a premium that the designer is typically restricted to incorporating only one large silicon chip set on board.
The PMC mezzanine, in contrast, has the real estate to provide much more flexibility. It's relatively easy, for example, to bring as many as four Ethernet ports off the front panel of a PMC board.
Making an informed choice between PC-MIP and PMC will depend on system requirements for speed and port count. At some level, the PCI bus begins to become a bottleneck and, with multiport designs, a PCI bus bridge is often required, adding yet another bottleneck. If a system requires four Ethernet ports, four single-port PC-MIP boards will have the performance edge over two dual-port PMC boards because of PCI bus issues.
For systems using mezzanine carrier boards, the advantage in port density goes to PMC, despite the fact that PC-MIP enables so many more mezzanine boards in the same physical space. A 6U PC-MIP carrier is capable of handling six Ethernet ports, routed to the rear panel, but only four ports if front-panel I/O is required. As for a carrier with two PMC sites, it can handle eight front-panel Ethernet ports, twice the port count possible with PC-MIP.
PC-MIP is also at a disadvantage for achieving bleeding-edge performance, and it simply cannot serve for those pushing the performance envelope to Gigabit Ethernet and even multiport Gigabit Ethernet. To do an efficient dual-port Gigabit Ethernet board requires a 64-bit, 66-MHz PCI bus. This wider, faster implementation of PCI is an option with PMC, but PC-MIP is limited to 32 bits. A 32-bit, 33-MHz PCI bus, whether implemented in a PMC or PC-MIP board, is incapable of handling the full bandwidth of Gigabit Ethernet, but can achieve only about 400 Mbits/s.
But even with a 64-bit, 66-MHz PCI bus, there are limitations. If a designer built a single-port board for the test or manufacturing-test environment, ignoring all the protocols, and pushed the board to its limits, it's possible to get nearly 1-Gbit/s throughput. But if a PCI bus bridge is added, that's going to create a loss of about 100 Mbits/s. If both a bridge and a second Ethernet port are added, the aggregate bandwidth of both ports will drop to around 700 or 800 Mbits/s.
Thus, even if a denser port configuration say, with four Gigabit Ethernet ports could fit within the constraints of a mezzanine board's real estate, this wouldn't make much sense performance wise because of the bottlenecks.
The mezzanine board designer must gauge what's to be gained by higher Ethernet speed and channel count if the board cannot manage the flow of data. At some point where the PCI bus becomes marginal, an on-board processor can help manage the data and get it efficiently out to the system. Bleeding-edge applications may require full-fledged Ethernet switch boards. These can be integrated into 3U- and 6U-size system boards, but not into a mezzanine.



