Getting a handle on fast backplanes

As backplane speeds move beyond 3 Gbits/second, the best cost/performance solution will involve evaluating choices in signaling and modulation, adaptive equalization, implementation efficiency, processes and advanced diagnostics.

The synergistic influence between the active and passive components of the transmission channel becomes increasingly important in interconnect design decisions at target speeds of 6 Gbits/s and faster. At these frequencies, manufacturing and environmental variations of the total interconnect system have a significant and often overlooked impact on end performance.

The collective synergy of these variations on the active and passive components involved comprises the implementation channel. Once the characteristics of the implementation channel are understood, effective transceiver technology design decisions can be made to account for them.

Characterizing a passive channel begins with determining its throughput or bandwidth. In the frequency domain this is determined by measuring the S21 of the channel-the amount of signal that can pass through the backplane at specific frequencies. This measurement quantifies the amount of loss due to trace skin effect, dielectric losses and underlying resonance structures caused by impedance mismatches.

Significant variation in performance occurs between signal layers in a backplane environment. As the layer connection moves toward the top surfaces of the backplane and interface cards, the S21 curve experiences more ripple. The amplitude of the ripple increases in frequency, ultimately limiting the bandwidth capacity of the channel.

In addition, specific backplane interconnect lengths are driven by the physical need to connect system elements (such as switch and line cards) together across the backplane. The most effective characterization data comes from focusing on S21 channel measurements on worst-case layers and lengths in the backplane.

There are three significant limitations to this data, however, forcing the designer to evaluate the channel data to an even greater extent than previously considered:

• This channel is not what the driver on the chip actually sees. Channel performance is affected by transceiver packaging effects and associated discontinuities.
• Channel data taken from test boards does not include characteristics of high-volume manufacturing variability.
• Channel data that is taken under controlled nominal environmental conditions do not take into account trace impedance values and channel-loss variation due to the effects of environmental conditions on printed-circuit board materials. These variations increase with channel length and frequency.

Manufacturing and environmental influences will cause bands of variance of the channel S21 data, depending on the architecture and the respective board materials used in a given system. The full extent of both variations must be individually quantified, with the amount of variation for either band increasing noticeably with frequency and channel length.

This variance band approach can be used to create a worst-case implementation channel, by offsetting the measured S21 by the worst-case variation over all conditions. Considering the frequency content needs of the transceiver technology relative to the performance of the implementation channel allows for better-informed transceiver decisions. As interconnect data rates move beyond 3 Gbits/s to 6 Gbits/s and higher, this system-level implementation channel approach becomes essential to achieve high yield and low cost.

Backplane interconnect building blocks fall into several categories. The implementation channel can help steer design decisions to result in the lowest power and cost when these trade-off elements are understood.

Understanding equalization

Transmit equalization is any element used to precondition the signal at the transmitter to optimize the received signal on the other end of the passive interconnect, resulting in more-reliable data transmission. Equalizer taps adjust the signal at specific times to shape it during transmission.

At speeds lower than 1 Gbit/s, transmit equalization is typically not required. At 2 to 3 Gbits/s a single tap is sufficient and at 6 Gbits/s, two to three taps are needed, with greater complexity used for links of 10 Gbits/s and higher.

Receive equalization is used at the receiver to allow valid data to be extracted from less-than-ideal received signals. Similar to transmit equalization, equalizer structures for the receiver vary with transmission speed. At less than 1 Gbit/s, receive equalization is typically not required. At 2 to 3 Gbits/s, a variety of simple filter structures can be used while at 6 Gbits/s and higher speeds, more-complex structures are required.

Setting the correct amount of equalization and optimizing it for a wide range of individual backplane interconnects affects reliability of data transfer, power and total system cost. At 2 to 3 Gbits/s, fixed equalization settings are typically used to establish a reliable interconnect. However, the trade-off is higher power consumption, because the extreme conditions of interconnect length and temperature typically result in a nominally higher amount of equalization being set.

Adaptive equalizers are automatically optimized based on external inputs reflecting the equalization needed for an individual channel. Adaptive receive equalizers self-generate this input to adjust settings at the receiver. A powerful approach for this is called decision-feedback equalization.

Adaptive transmit equalizers require an external input from the corresponding receiver on the other end of the backplane interconnect to arrive at the best settings for the situation. To accomplish this, a method of communicating information from the receiver to the transmitter is used.

Signaling and other issues

There are two approaches to backplane signaling. Binary signaling is the traditional, and most widely available, signaling and modulation method for backplane-interconnect transmission. Multilevel signaling has been used in standard interconnect applications such as digital subscriber lines for years, and has recently become available as an additional transceiver signaling option for backplane applications.

Implementing multilevel signaling results in an equivalent reduction in the frequency of transceiver operation for a given data rate, because more bits are transmitted for each clock cycle. This results in significantly reduced signal sensitivity to implementation-channel characteristics due to transceiver operation at half the frequency. However, there is less overall transmit voltage available between logic levels, as the signal is sliced into four levels vs. two. Thus, multilevel signaling can offer advantages for cases where the implementation channel has a steep slope.

Implementation efficiency is a measure of actual transceiver product performance compared with the promised theoretical performance. When evaluating potential transceiver approaches, technical risks must be weighed against expected implementation efficiency. This is especially true at speeds greater than 3 Gbits/s, with implementation efficiency falling sharply as speeds approach 10 Gbits/s due to the magnified effects of circuit and process.

Integrating diagnostics into the transceiver itself provides a comprehensive and nonintrusive alternative to the use of traditional external test equipment that, by its physical nature, can alter the test results. For speeds of 6 Gbits/s and higher this diagnostic testing becomes crucial. At 10 Gbits/s, it is essential.

Efforts at standardization are under way for binary-signaling implementations across backplanes. The need for similar efforts for multilevel signaling is growing with the migration to higher speeds over more realistic implementation channels.

Bill Hoppin is vice president of marketing at Accelerant Networks Inc. (Beaverton, Ore.) and John D'Ambrosia is manager of semiconductor relations at Tyco Electronics Corp. (Middletown, Pa.).

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