PCI Express eases pc board layout tasks

The quest for ever-higher bandwidth has brought us inevitably to high-speed serial technologies such as PCI Express, which runs at a symbol rate of 2.5 Gbits per second. This hunger for bandwidth has put designers firmly into transmission-line territory, previously considered the domain of others. But PCI Express design has thoroughly addressed transmission-line issues and has succeeded in greatly streamlining printed-circuit board layout at these multigigabit rates.

PCI Express provides a variety of features to make pc board layout much more straightforward. All connections are strictly point-to-point, with no need for stubs or multidrop topologies. Since the clock for every differential pair is embedded in the signal, skew requirements between differential pairs can be greatly relaxed. PCI Express traces are terminated on-die, which relieves the pc board designer of some delicate work and greatly improves signal integrity. With the termination resistor on-die, the parasitic resistance, inductance and capacitance between the termination point and the signal source/destination are as small as possible.

Two of the most common layout errors are reversing the polarity of differential signals and reversing the order of bused signals. These can have serious effects on a project's schedule and cost. PCI Express addresses such errors with polarity inversion, which is required, and lane reversal, which is optional.

From a board layout point of view, PCI Express is very simple: All information is transmitted over differential pairs. Board layout only rarely needs to be concerned with the complexities inherent in high-speed, single-ended buses.

As we will see, there are many layout issues to be satisfied, but every differential pair can be examined in isolation from all other differential pairs. It would take an extreme pc board layout to create a skew between differential pairs that approached the tolerances of PCI Express.

A fairly lengthy list of board layout considerations has already been well-documented in industry literature. While these could be used in a checklist fashion, pc board designers should understand the few electromagnetic effects that make these layout considerations important:

• Loss is the degree to which a differential signal is attenuated from transmitter to receiver. It is proportional to trace length and signal frequency, and inversely proportional to trace width. Vias and connectors also contribute to loss. All loss budget must be calculated for every differential pair.
• Jitter is the variation in the edge's arrival time at the receiver. PCI Express allows a budget of 0.3 unit interval (UI), where 1 UI = 400 picosecond, which is the period of PCI Express' symbol rate of 2.5 GHz.
• Crosstalk is the coupling of energy between signals, and there are both far-end and near-end forms. For PCI Express, crosstalk is only a consideration between differential pairs and can be controlled by the physical spacing between these pairs.
• Mode conversion refers to the transformation between differential and common-mode voltages. It is generally created by imperfections in the pc board material due to manufacturing tolerances, such as the varying alignments between the two traces of the differential pair over fiberglass bundles and/or resin-rich areas or resin troughs in the board dielectric.

Differential trace impedance is not as important to PCI Express as loss and jitter. Nevertheless, a target of 100 ohms plus/minus 15 percent is desirable, although that could vary slightly depending on the design rules, manufacturing tolerances and number of pc-board layers. This impedance will also change based on the variations in plating or solder-mask thickness, over or underetching of microstrip traces, and other imperfections.

From our simple layout philosophy comes the most basic rule for layout of PCI Express differential pairs: Whatever is done to one trace in the differential pair, the same or its mirror image must be done to the other trace. To put it another way, the two traces must always be equal or symmetrical.

Layout issues

Within a differential pair, trace lengths must be matched to within plus/minus 5 mils. While serpentines are no longer needed, other techniques must be used to match trace lengths. A bend in one direction must be followed by a bend in the opposite direction. Links mismatches imposed by package pins or connector pins must be compensated for as close to the mismatch as possible.

Intelligent placement of signal pins by vendors will simplify package breakout. As the figure shows, side-by-side routing is clearly the most symmetrical, but adjacent and diagonal routing are also acceptable.

Locate the ac-coupling caps close to the transmit pins, and be sure to place and route them symmetrically. The best size is 0402, but 0603 is acceptable. Do not use 0805 or C-packs.

Avoid sharp or 90 degrees bends, and remember that a bend in one direction must be followed by a bend in the opposite direction to maintain trace-length matching.

Always maintain an unbroken ground reference plan under PCI Express differential pairs. This will minimize EMI and crosstalk, and also provide a return path, since even differential signals experience high-frequency common-mode noise requiring a return path. There should be a generous clearance between traces and voids in the ground plane, to minimize edge effects. Use stitching vias for layer transactions, and avoid routing traces over anti-pads.

Vias contribute up to 0.25 dB each. The recommendation is to use a pad size of less than 25 mis and a hole size of less than 14 mils.

PCI Express specifies a new connector with a standard PTH whose pinout is optimized for differential routing. A reference plane should not be placed under edge finger pads, to maximize impedance and loss performance.

If your first PCI Express pc board works, then you will want to know how well it works. If it doesn't work, then you need to know why. In either case, you need test points. These must be placed with PCI Express traces, not at the end of stubs that tie in to the traces. It is recommended that a ground pad be placed beside every test point to support single-ended probing.

The simulation and validation of PCI Express layouts is a complex topic unto itself. Suffice it to say that simulation is highly recommended. IC vendors should supply simulation models and simulation examples.

Layout and routing of any gigahertz-class signal will never be trivial, but the design and features of PCI Express make those tasks relatively straightforward. They can be reliably and successfully pursued based on a small set of fundamental concepts and a manageable number of clear guidelines.

John Beaton is interconnect manager for the Network Processing Group at Intel Corp. (Hillsboro, Ore.).

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