10-Gbit backplanes require new metrics

Numerous communications and information system companies, buoyed by the economy's recent quasi-recovery, have initiated projects to push system speeds to the next frontier. Engineers once again are trying to figure out how to bypass hurdles born of performance issues rather than cost goals, which had dictated product development during the industry's downturn.

Many of the new R&D efforts target higher aggregate data rates. This shift is initiating a healthy debate about how fast systems can be made to run, and the technologies required to get there.

Copper backplanes used in high-end communication systems are one key focus of heightened attention and activity. The earlier generation of systems took a major step by moving from the traditional parallel or bus-based backplanes to high-speed serial backplanes running at 1 to 3 Gbits/second. Today's high-speed serial I/O technology can handle data at more than 10 Gbits/s.

The availability of 10-Gbit/s I/Os for chip-to-chip and backplane applications is providing system designers with a new realm of possibilities in architecting next-generation systems. The high-speed serial momentum is also very visible in various industry standards organizations, where new serial standards are being defined for the 5- and 6- Gbit/s range as well as 10 Gbits/s and beyond. Indeed, leading-edge system companies are now taking serial backplane data rates higher than 10 Gbits/s.

The move to drive faster data rates over copper backplanes is providing the industry with a few major engineering challenges. First-order issues involve pc board losses, impedance mismatches at the mechanical discontinuities and crosstalk between neighboring channels.

It is essential that engineers fully understand these electromechanical factors to design an effective signaling environment. The industry is addressing the problems at many levels and from a variety of directions-connector suppliers, backplane makers, tool providers, semiconductor companies and system houses. Collaboration among these groups will be the key to success.

The connector and connector-board interface play major roles in backplane interconnect systems because of reflection and crosstalk. In 10-Gbit/s systems, stub length must be minimized, while connector near-end crosstalk (pair-to-pair transfer) must be controlled to within -35 to -40 dB or less at 5 GHz. Several new 10-Gbit/s connectors have shown excellent performance in both evaluation platforms and volume-production systems.

Pc board losses are also of major importance at 10 Gbits/s. In a typical backplane, conventional FR4 can shrink a signal by 30 dB at 5 GHz. New, low-loss dielectric materials, available from several suppliers, can go the same distance with only 15 dB of attenuation.

Low-loss material can be sandwiched with FR4 to put the low-loss traces only where they're needed. The addition of the low-loss material is expected to increase backplane cost by only about 15 to 25 percent. The price and availability of these materials is becoming less of a concern as they become more common.

Another key element to passing high-frequency signals over a backplane is minimizing the effect of via stubs. Stubs can be eliminated through back-drilling, also known as counter-boring, or with other advanced manufacturing techniques such as blind, buried or micro vias.

Semiconductor transceiver technology is also reaching new performance levels. The most significant aspects, other than the raw speed, are pre-emphasis and equalization capabilities.

In pre-equalization or pre-emphasis, the serial signal is selectively emphasized or de-emphasized at the transmitter. At 10 Gbits/s, however, equalization/emphasis only at the transmitter makes data recovery difficult for traces longer than 20 inches. As a result, post-equalization circuits are being designed into receivers.

The programmability or adaptability of pre- and post-equalization lets the engineer optimize transceiver settings individually for each serial channel. Devices are coming to market with programmable equalization to provide solutions for long-reach 10-Gbit/s serial backplanes.

The availability of these technologies is allowing engineers to design new classes of systems based on 10-Gbit/s signaling. To fully understand the complexity of transmitting data at such frequencies, advanced evaluation platforms and reference designs need to be carefully engineered and thoroughly analyzed.

The engineering and analysis processes are being performed through technology partnerships involving semiconductor, connector and backplane companies, as well as systems companies. Models created from these platforms and production backplanes are used repeatedly for channel simulations and correlations.

Using such a partnership strategy, Xilinx has developed a complete characterization methodology for analyzing backplane performance from 1 Gbit/s to more than 10 Gbits/s. Jointly working with industry partners, Xilinx has characterized and benchmarked a variety of configurations. The knowledge gained throughout this process is being used today as a baseline for new 10-Gbit/s backplanes.

The following example provides a simplified overview of the methodology used to analyze backplane performance. The backplane characterized in this example has both mesh and dual-star architectures with a maximum trace length of 24.5 inches. The 22 x 11-inch back-drilled backplane is more than 200 mils thick. It uses a combination of a low-loss material and standard FR4, along with 10-Gbit/s low-crosstalk backplane connectors.

In this example, designers should first measure through (forward-transfer) performance of various backplane channels and plot the logarithmic gain (dB) vs. frequency. Then, they should select the receiver equalization with a gain-vs.-frequency response that is the inverse of the measured channel.

Next, engineers should measure near-end crosstalk (forward transfer) on all adjacent aggressor channels in the connector. That includes vertical, horizontal and diagonal measures in a connector with pairs arranged in a rectangular grid.

Then, engineers can choose the one with the largest magnitude at half-baud frequency for worst-case simulations. Using the above measurements, the signal is simulated through the complete channel, including the effects of crosstalk and equalization.

This methodology has proven very powerful in analyzing a variety of backplane configurations from our partners and customers. Dozens of board and connector configurations have been successfully analyzed and refined through these methods.

As expected, some configurations perform better than others, but all can be studied for design strengths and weaknesses. In the end, the process clearly shows today's technology is providing systems companies with effective solutions for implementing robust 10-Gbit/s serial backplane designs.

Communications system companies around the world are adopting these new technologies to design state-of-the-art systems that will establish them as performance leaders among their peers.

Tim Hemken is marketing director for the Communications Technology Division at Xilinx Inc. (San Jose, Calif.).