Design Article
Packaging SoCs
5/23/2003 6:56 AM EDT
Packaging SoCs
Packaging concern: signal integrity issues rise with 500 Mbit/sec rates
More functions require balanced SoC design
Nanometer SoC complexities require more work in silicon, package co-design
Systems-on-programmable chips: A look at the packaging challenges
Co-design or bust: SoC FBGA packaging
SoC goal staying alive: lowest cost, smallest size
Design rules push SoC packaging to the forefront
The rise of system-on-chip devices, along with the challenge of 130nm design rules and the looming challenge of 90nm design rules has, and will continue to, test old methodologies and, more often than not, force them into retirement.
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