Net processors address multiservice switch demands

The multiservice switch market has technology requirements that are significantly different than those faced in past years during the unprecedented buildup of services at the 10 to 40 Gbit/sec network core.

The market is diverse with single multiservice platforms accommodating a mixture of ATM, Frame Relay, IP, Multi-protocol Label Switching (MPLS), Packet over SONET (PoS), and Gigabit Ethernet. Interface speeds range from subT1/E1 to OC-3 to full-duplex OC-48c/STM-16 links. The multiservice switch must also be able to adapt to emerging applications at the network edge such as packetized voice (VoIP) and 2.5G/3G wireless backbone networks. In addition, with converging applications (data/voice/video) come more extensive requirements for Quality of Service (QoS).

One technology used by network equipment manufacturers to help address the issues of multiservice switch design is the network processor. Network processors (NPUs) provide a programmable solution for the forwarding plane, enabling more flexible and scalable implementations. In addition, development time and costs are generally less as compared to the more traditional ASIC-based designs.

A multiservice switch is generally defined as a platform that can handle more than one protocol (usually ATM and Frame Relay, along with other protocols including IP, MPLS, PoS, Gigabit Ethernet, TDM, and legacy data) and can provide aggregation and bandwidth-efficient uplink capabilities.

The traditional architecture of a multiservice switch is a rack or shelf with multiple flavors of line cards and one or more control processor cards — all connecting through a backplane interconnect or fabric. These line cards are usually dedicated to a specific service such as ATM, Frame Relay, TDM, or IP. Routing within the shelf across the system backplane or switch fabric provides interworking among the cards.

There are two general categories of processor cards: control processor cards and functional processor or line cards. The control processor card manages and controls applications supporting both system and networking functions. It provides shelf management functions, such as monitoring and alarm processing, and it connects to a network management system. The control processor card also interacts with the line cards, providing common services.

Redundancy is implemented by adding another control processor card. Line cards are responsible for terminating the physical connections and for processing the specific Layer 2 and higher protocols, including ATM, MPLS, PoS, Frame Relay, and IP. Inter-working among protocols is achieved by routing traffic to other protocol-specific line cards as needed, thereby allowing the architecture to be multi-service at the system level. Other items included on a typical line card include LIU/Framers to transmit/receive data, host processor, and a backplane or switch fabric interface logic/chip.

Some architectures may also use TDM and packet/cell switch fabric line cards. Fabric solutions usually include one or more fabric chips that reside on one or more central switch fabric cards. Additional fabric interface chips generally reside on the line cards, bridging traffic from an ASIC or ASSPs to the fabric itself.

Ranges of speed for switch fabrics vary from 20 Gbit/sec to terabits per second. Another approach to switch fabrics is a mesh backplane. A mesh is an open architecture, distributed fabric where each node has both a 1 by N switch to transmit traffic to other nodes and N-1 point-to-point connections to every other node for receiving traffic. For switches not requiring massive backplane speeds, mesh fabrics provide a very cost-effective solution.

Traditional multiservice platforms typically use line cards based on in-house ASIC development or application-specific silicon. These line cards are usually dedicated to a single service, such as ATM or Frame Relay, and have a set number of interfaces that they can support. Space and cost become an issue when service providers are faced with adding another chassis or platform to accommodate expansion.

Consolidation crucial

To maximize ROI for network equipment manufacturers and service providers, consolidation of multiservice switch technologies is becoming key. Merging interfaces and protocols and adding greater density per line card - all while reducing board components, power consumption, and costs — is a tough challenge with traditional ASIC-based or ASSP designs. In addition, new and evolving services must be provided to keep pace with end-user demands. One of the greatest challenges is to be able to scale the platform to adapt to changing requirements and standards over time without major disruption to the service provider network.

Increasing interface density and bandwidth has been an ongoing challenge for network equipment manufacturers. It is not uncommon today to see systems providing up to 32 ports of T1/E1, where two years ago the standard was four or eight ports per line card. Likewise, bandwidth capacity of these systems has seen a steady increase. Two years ago, the most common range of speed interfaces was from T1/E1 to OC-3 (maximum).

Today, these systems must support speeds from channelized DS0 to OC-48c - and even OC-192 in some cases (although numbers of shipments are low for this speed). The Dell' Oro Group calculated that DS3 and OC-12, particularly the channelized versions, will be the primary bandwidths for connecting enterprises at the network edge to the service provider networks, while OC-48 and above will be limited to 3% of total ports shipped in 2006 (see Dell'Oro Group 01/28/02 Switches & Routers Report). Bottom line: the challenge is to provide scalable line cards that offer a range of speeds and provide the necessary interface density to address the multiservice switch market space.

The traditional design of a single protocol line card is also under the gun in today's environment. More vendors are delivering multi-protocol capabilities on a single line card. Popular examples include ATM/IP and IP/PoS on a single line card.

And, adaptability is key in keeping up with evolving standards and market requirements. Examples of evolving protocols and standards include RFC 2684 (describing AAL-5 encapsulation methods) replacing RFC 1483, and the migration from IPv4 to IPv6. Furthermore, once the design is released to market, the limited flexibility of hardware-based product designs severely restricts the ability to adjust or add product functionality.

There is an ever-increasing requirement for complex multi-protocol processing and intelligence at the access and edge of the networks. Scalability, adaptability and flexibility are required in order to address these requirements. The challenge for network equipment manufacturers is to facilitate these requirements in a dynamic environment while ultimately providing improved ROI and cost efficiency.

One line card using an NPU can displace previous solutions consisting of two or more cards — at a lower cost then the previous line cards. Multiple protocols can be combined on a single line card along with increased port density if needed. With an NPU implementation, you are able to eliminate extra logic (such as ASICs, ASSPs, SARs, Framers, and FPGAs) resulting in significant savings per line card. The level of integrated functions on the NPUs reduces part count, which in turn means less power, space and bus interconnects. For example, Motorola's NPUs have built-in Ethernet MACs, SONET Framers, SARing capabilities, classification coprocessor, buffer management, fabric control, and host control.

Architectural variation

NPUs may differ architecturally in how they handle various functions. One model is the processor+coprocessor model wherein processors handle much of the services processing, but hardware acceleration is provided for computationally intensive functions through integrated coprocessors. Other models offer micro-engine farms that may be programmed for all functions or in some cases require the use of external coprocessors.

QoS is a key mechanism in multiservice applications where the convergence of services requires appropriate levels of transmission quality for various types of applications such as VoIP, streaming video, Web casting, or data transfer. Technologies such as ATM, IP DiffServ (Differentiated Services), and MPLS have been developed in order to facilitate the deployment of QoS across networks by providing sufficient QoS differentiation and ease of management and provisioning while maximizing overall network utilization. These QoS technologies may be supported to some degree on the NPU (called soft queuing) or they may require an external traffic management coprocessor (TMC) to offload the complex algorithms and buffering mechanisms involved in fine-grained QoS.

Key requirements of TMCs in supporting multiservice applications include multi-protocol support (standard and non-standard), micro-level QoS controls, flexible scheduling hierarchy, buffer management, fully configurable service level agreements (SLAs), and high-level APIs for ease of programming and investment protection. These requirements can be addressed in a product such as Motorola's Q-5 TMC, designed as look-aside traffic manager to the Motorola NPUs. The Q-5 TMC offers 5 Gbit/sec of multi-protocol support for any protocol, including ATM TM 4.x, IP DiffServ, IntServ, MPLS, Ethernet, PoS, and Frame Relay.

See related chart

See related chart