PCI mezzanine cards allow for scalable networking designs

Upgrades tend to minimize the impact on system stability, where system downtime translates into lost revenue and irate customers. New equipment is typically considered only when it offers a quantum improvement in both performance and reliability — in short, improved margin of operations.

Processor mezzanine architectures such as IndustryPack, PC MIP, and PCI Mezzanine Card (PMC) are ideally suited to fill that need. But designers of systems and subsystems must break away from outdated monolithic design models and focus more on modularity. To minimize the cost and development interval, only the components that truly define a company's differentiation in the market should be developed internally; the remainder should be built out with standard components.

Designing a wide range of telecom and networking infrastructure systems with the modular mezzanine approach can free up valuable board space and improve the product's service lifetime by permitting an upgrade in processing capacity without a full product replacement.

The advantages of this approach can most clearly be seen in Universal Mobile Telecommunications System (UMTS) 3G cellular networks. The highly complex protocol suite needed to achieve service richness and flexibility has led to a significant and expending processor load. In order to remain competitive, several key equipment vendors have forecast the scaling of processing capacity as more than doubling every 18 months.

Consider the following provisioning scenario. The vendor has a carrier board that supports six PMC sites and has a requirement to upgrade the processor PMC modules to obtain a threefold performance improvement. To achieve a performance improvement of three times with the incumbent PMC, the total hardware would have to increase by a factor of three, with a corresponding threefold increase in floor space. Simple arithmetic points out that even if the threefold-performance-upgraded PMC doubles the price, the overall system cost still decreases by one-third compared with the incumbent PMC plus the saving in floor space. Typical price changes for three-times performance growth would be 50 percent to 60 percent higher than the incumbent PMC, given historical values on Moore's MIPS-per-dollar curve.

Industry standards defined by the VME Industrial Trade Association (VITA) and PCI Industrial Computing Manufacturers Group (PICMG) ensure common, compatible interfaces for processor and nonprocessor PMC modules. The structure of bus interfaces from the carrier board to the PMC renders the processing engine practically indistinguishable from an on-board processing system. To carry data traffic, local PCI or PCI-X interfaces are currently used in addition to specific functional buses, including H.110 time-division multiplex (TDM), Utopia and POS-PHY buses. Emerging changes to PMC standards expand carrier and mezzanine connector definitions to extend existing Ethernet MDI links, in order to support dual 1000-BT Ethernet through the Jn4 connector.

With the introduction of high-speed network interfaces on PMCs, the importance of the PCI bus to carry computing payload has begun to diminish in favor of Ethernet network inter-connect. Inclusion of Layer 2 or Layer 3 packet switches on the carrier board or on an off-board hub offers a much higher traffic capacity and more flexible inter-connect between processing engines. Network-based interconnect facilitates the incorporation of high-availability (HA) compute capability into areas not traditionally served by HA.

The traditional limiting factor in implementing HA computing on standard platforms has been the physical form factor and the associated bus structure, which forces a specific physical design to permit control switchover to a redundant unit. The combination of PMC technology and network interconnect mitigates the key physical dependencies required for redundant processing units to execute a warm takeover.

Support for extensions
Proposals for supporting the Intelligent Peripheral Management Interface (IPMI) over Ethernet links rather than the traditional I2C bus will allow selected IPMI maintenance functions to be extended to PMC modules without the need for a local I2C bus or even a host IPMI driver on the carrier board. Emerging standards such as PICMG 3.x propose to offer packaging and functionality to support mezzanine-level hot-swap capability.

With processor PMC technology in place, designers are presented with a wide variety of system options. For example, CompactPCI form factor carrier boards supporting dual PCI-bridged PMC sites are available today. These blades typically conform to the PICMG 2.x standards set that includes support for IPMI and hot-swap capability.

The newer versions support on-board multiport Gigabit Ethernet switches, which connect the PMC sites to each other and to the external network, either through the backplane (as defined in PICMG 2.16 definition) or through external connectors (EM or optical links).

By combining dual-processor PMC modules on the dual PMC carrier board, the system designer can assemble a four-processor cluster on a single 6U standard board. By combining a number of carrier boards in a PICMG 2.16 standard shelf, a much larger cluster can be assembled. The CPCI (6U) form factor is used as an example because of its broad industry acceptance as a blade configuration, but multi-PMC clusters can be developed using a wide variety of standard and proprietary form factors.

Groups of single- or multiprocessor modules connected on the network can be configured as discrete or load-shared compute engines in an asymmetric multiprocessing (AMP) computing model. AMP clusters are typically organized as functionally or load-partitioned systems and rely on RTOSes like VxWorks or QNX to execute separately on each processing element in the cluster.

For dual-processor elements, the RTOS manages a common memory between both processors via the MMU. Using the same physical organization, processor groups can form low-cost, small-footprint symmetric multiprocessing (SMP) clusters. The cluster is, of course, limited by interconnect network performance to achieve effective cache coherence timing.

For SMP configurations, specific versions of Linux support SMP operations. Load-shared AMP and SMP clusters inherently function as highly available systems, which can be formed out of a set of basic off-the-shelf building blocks.

General-purpose processors are not the only processing systems being developed on the PMC form factor.

DSP "farms" that support vocoding and compression applications are already available in PMC form factors and conform to PMC's maximum power dissipation levels but typically don't conform to PMC pinout standards. Development of fully compliant PMC-based DSP "farms" are already under way by a number of embedded vendors.

Using the available H.110 (TDM) bus or Utopia bus technologies coupled to the new Gigabit Ethernet connectivity, a voice-over-packet conversion can be formed on a single PMC module. When this VoP PMC module is placed on a carrier board, such as the 6U CPCI unit described earlier, and is accompanied by a general-purpose processor PMC supporting network and/or access signaling software, a VoP gateway becomes available on a single CPCI blade.

Higher-end network processors such as Intel's iXP2400 dissipate 10 watts (typical) and are therefore within the power envelope for development on a PMC form factor. By combining these PMC options on a standard carrier board, the system designer can construct a wide variety of high-performance blades to serve as VoP gateways, network monitor or sniffer systems, router line interfaces and a large number of high-performance, high-reliability computing configurations.