Simulating the XFP Electrical Interface: Part 2

As the XFP module architecture gains headway in the optical networking and datacom sectors, simulation of electrical performance becomes extremely important for design engineers. Specifically, running electromagnetic (EM) field measurements provide designers with strong insights into the overall electrical capabilities of XFP modules.

This is Part 2 in our series on simulating the electrical performance of the interconnect for XFP module applications. In Part 1, we provided an overview of the spec and provided insight into using EM simulation on the XFP printed circuit traces. In this section, we'll cover EM simulations for the connector and BGA package. We'll also look at end-to-end channel simulations.

Characterizing the Connector
The XFP host connector used during out simulation is based on a 0.8-mm pitch, 30-position right angle connector such as the 788862C manufactured by Tyco. This connector geometry was originally designed for SFP applications and data rates of 2.5 Gbits. Receive data (RD) and transmit data (TD) are the only high-speed nets. Both use a ground-signal-signal-ground (GSSG) topology and are located on the outer edge of the connector.

Below we'll show how EM simulation can be used to characterize the electrical performance of this connector. Full-wave, 3D EM simulation of the connector at GHz frequencies can be very computationally intensive unless appropriate model reduction efforts are performed. It is important to include only those structures that have significant effect on the electrical performance.

During our characterization of the connector, 2D quasi-static simulations were performed on various cross-sections of the connector to establish baseline pin-to-pin electromagnetic coupling. Results from these simulations allow the designer to reduce the model geometry to include only those pins that are relevant. Full-wave, 3D simulations were also performed on the reduced geometry so that S-parameters could be extracted.

Figure 7 depicts the Tyco 788862C connector in 3D and a cross-sectional views. The high-speed traces are located on the top surface of the transceiver board and propagate along the upper pins in the connector.

Two cross-sections were considered for 2D EM simulation and model reduction. Figure 8 depicts the cross-sections used for the analysis. Cross-section 1 cuts through the pins in a plane parallel with the host board and cross-section 2 cuts through a perpendicular plane. The cross sections were chosen along regions of the pins that are relatively uniform. A 2D quasi-static electromagnetic (EM) field simulator based on the finite element method (FEM), was used for the simulations.

Figure 9 contains EM field (H-field) plots for the two cross-sections depicted in Figure 8. The field plots show that the electromagnetic field decays by at least 50 dB within 4 pins. From this result, designers can conclude that four pins are sufficient in the 3D modeling. Figure 10 depicts the reduced geometry that was used for 3D electromagnetic modeling. Only 4 of the 30 pins are required for accurate results.

The electrical performance of the connector is not independent of the mechanical implementation on the host board. Mounting pads and their geometry have a significant effect and are included in the 3D simulations that follow. In XFP implementations, there is a mechanical cage assembly that is also a consideration, especially for electromagnetic interference (EMI), but is not included in the results shown here.

A close-up view of the host board side of the connector is shown in Figure 11. The high-speed differential traces are excited using a gap source port; a similar approach is applied on the transceiver board side of the connector.

Full-wave, 3D EM simulations were performed using a high frequency structure simulator (HFSS). Eight adaptive passes were performed to arrive at a final mesh containing 87,000 FEM tetrahedra and an S-parameter convergence within 1%. Two cases were considered: Case 1 is the connector in isolation; Case 2 is the connector plus PCB pads and vias to ground as shown in Figure 11.

Figure 12 is a plot of the extracted S-parameters for case 1 and case 2. As designers can see from Figure 12, the connector in isolation (Case 1) has better than 20 dB return loss up to 8.5GHz. This performance is more than sufficient to support the overall channel budget highlighted in Chapter 2 of the XFP Specification.

The addition of the mounting pads (Case 2) has a significant effect on the overall connector performance as seen by the S-parameters in Figure 12. The mounting pads modify the differential impedance and reduce the bandwidth of the connector.

Figure 12 also shows a resonance occurring at 10.82 GHz. Indeed the resonance is quite pronounced for the isolated geometry (Case 1). Examination of the electromagnetic field provides insight into the mechanism causing the resonance.

Figure 13 contains H-field plots at 5 GHz and at 10.82 GHz that illustrate mode conversion from a differential- to a common-mode occurs at the higher frequency. This mode conversion is the cause of the resonances found in Figure 12. In subsequent simulations it was found that replacing the grounding vias with a solid conductor completely eliminated the mode conversion. Designers should consider using more than just two vias along the ground pads to eliminate the mode conversion.

Analyzing the XFP Package
As mentioned in Part 1 of this article, the XFP calls for a BGA package. Like the overall connector, running detailed simulations of this BGA package is vital to the development of XFP transceiver modules.

Figure 14 shows an analysis of the XFP BGA package using a full-wave EM field simulation. The structure has a four-layer stack-up with a ground plane base, V_SS and V_dd voltage waveform planes, and a top-layer signal plane. Wirebonds are used to provide the electrical connection between the package and the chip die.

Figure 15 depicts the 3D model from an HFSS tool. Careful inspection of the model will reveal that all four solder balls have been configured as ports. At high frequency, the voltage source waveforms V_SS and V_dd are electrical grounds and are often omitted from the high-frequency analysis. In this model, however, V_SS and V_dd solder balls were configured as ports so that power bounce analysis can be performed. The terminal ports T1 and T2 carry the high-speed differential signals. On the chip side of the package, gap source ports have been placed between each wirebond and ground.

A frequency sweep was computed from 100 MHz to 50 GHz. This particularly wideband sweep was performed so that transient results can be computed for 24-ps rise times. For proper system operation it is important to maintain the source voltages within a narrow range; source voltage bounce due to switching transients on signal traces can lead to signaling error. The transient simulations of the BGA package revealed 2.2% peak-to-peak voltage bounce at the chip for V_dd, and 2.6% peak-peak bounce at chip for V_SS. These values for power integrity are quite low, but careful system-level analysis should be performed to ensure that cumulative effects are within specifications.

Figure 16 is a plot of the differential transmission SDD21 through the BGA package. The insertion loss is very low over the critical region between DC and 6.5 GHz. It is within this frequency range that over 80% of the digital signal energy resides.

Figure 17 is a plot of the differential return loss SDD11 and SDD22 on the solder ball and wirebond sides of the BGA package, respectively. Both the transmission and reflection plots reveal that the package exhibits minor resonances at frequencies near 7, 14, and 26 GHz.

End-to-End Channel Simulation
In all of the sections above and in Part 1, circuit simulation, EM simulation, and combinations of the two were performed to extract S-parameter models. It is desirable to combine these results in a single simulation to examine the end-to-end performance of an XFP implementation. A convenient method for combining these results is to use a high-frequency system simulator. Not only can the system simulator provide the frequency domain results for the system, but also transient results and system-level metrics such as eye diagrams and bit-error-rate (BER) plots.

Figure 18 depicts the system simulator model for the XFP channel of Figure 2 from Part 1 including the transceiver board traces, the connector, the host board traces, and the BGA package. S-parameter models that were computed from the circuit and EM simulations are cascaded to allow evaluation of end-to-end system performance.

Figure 19 contains simulated transmission (SDD21) and reflection (SDD11) of the end-to-end system. The simulated performance only just meets the overall XFP system budget of 6.5-dB channel insertion loss at 5.5 GHz; performance meets the 10-dB return loss specification from 1 MHz to 7.5 GHz.

Figure 20 is a diagram from the XFP specification that depicts compliance points for electrical performance. Compliance points A and D are used for ASIC/serdes compliance and hence are only informative for the purposes of XFP host or module design. Compliance points B, B', C, and C' have strict specifications that must be met for host and module designs.

Eye diagrams were generated by the system-level simulation of the end-to-end system of Figure 18. Figure 21 depicts an eye diagram at compliance point C while Figure 22 depicts an eye diagram at compliance point D.

As can be seen from figures 21 and 22, the connector design under investigation fails compliance at point C. Upon further investigation, it was found that the main contributor was the return loss of the 30-pin connector. One must remember that the connector used in these simulations was originally designed for lower-speed, 2.5 Gbit/s SFP applications. Tyco Electronics has since redesigned the connector specifically for XFP and has improved the connector return loss by over 6 dB at 8 GHz. It is expected that the new design will meet compliance easily; the new connector will be simulated in the near future.

Wrap Up
The XFP MSA has defined a data agnostic, small form factor pluggable transceiver module for 10 Gbit/s optical communications. It is generally expected that this new form factor will outpace all others and will provide the ultimate solution for high-density datacom and telecom transmission systems. The most prominent feature of this new module is that it does not contain an integrated transceiver ASIC. Instead, the transceiver is placed out on the host board where additional functionality and integration can be achieved. With the transceiver on the host board, it becomes necessary to transmit 10Gb/s data signals across 8 to 12 in. spans of lossy FR-4 PCB. Design of the high-speed interconnect on these boards requires special attention to ensure signal fidelity.

In this article, several critical elements of the XFI channel were considered along with an end-to-end system simulation. It was shown that with proper design practices and application of simulation, designers of optical communication system products can achieve 10 Gbit//s transmission on traditional printed circuit boards.

Author's Note: The authors extend gratitude to Ali Ghiasi of Broadcom Corporation for providing the transceiver and host board geometries and measurements; Michael Fogg of Tyco Electronics for providing the 3D geometric model for the 30-pin connector; Daniel Wu of Ansoft for the microstip trace loss simulations; and Eldon Staggs of Ansoft Corporation for the end-to-end system simulation.

Editor's Note: To view Part 1 of this article, click here.

About the Authors
Lawrence Williams is director of business development at Ansoft Corp. He received his Masters, Engineers, and Ph.D. degrees from UCLA . Lawrence can be reached at williams@ansoft.com.

Steve Rousselle is an applications engineering manager at Ansoft Corp. He received a BSEE and MSEE degrees from Michigan Technological University. Steve can be reached at srousselle@ansoft.com

Bryan Boots is an application engineer at Ansoft Corp. He received a BSEE and MSEE from the University of Colorado, Boulder. Bryan can be reached at bboots@ansoft.com.