Keep Your Eye On RapidIO

Developed by Motorola in collaboration with Mercury Computer Systems, the RapidIO architecture was officially launched in late February during the Embedded Systems Conference Spring 2000 (Chicago). Since then, the proposed open standard for embedded I/O processing has gathered endorsements from about a dozen manufacturers, ranging from semiconductor companies to network OEMs. The latest company to join the newly formed RapidIO Trade Association was SKY Computers, a competitor of Mercury Computer (and another manufacturer of embedded processing systems).

The RapidIO interconnect architecture was designed to provide network and I/O performance levels scaling to 10 Gbits/s and beyond. The high-performance packet-switching architecture is similar to technology developed earlier by Mercury and SKY. However, endorsement by semiconductor companies on the supply side and acceptance by networking power houses on the demand side should ensure the availability of inexpensive silicon for critical bridges and interface circuits. Architecturally, the proposed open-standard is very versatile. With suitable interface or bridge circuits, it can be used to upgrade or complement all sorts of existing embedded systems (e.g., boards using the PCI-X bus) and proposed I/O protocols (e.g., the InfiniBand architecture supported by Intel, Compaq, and others).

Industry analysts have been impressed by the strong support RapidIO has already received from the key networking OEMs-companies like Cisco Systems, Nortel Networks, Lucent Technologies and, of course, Motorola. Analyst Shannon Pleasant, Director of the Voice and Data Communications Group at Cahners In-Stat, noted, "Motorola's long heritage in the communications silicon market and the backing of the major systems players will be a strong force behind the adoption of the RapidIO interconnect architecture as an open standard." In turn, the endorsement by the networking OEMs attracted more semiconductor companies (including Tundra Semiconductor, Seagull Semiconductor, and Xilinx) who want to become chip suppliers.

The network OEMs like the plan to make RapidIO an open standard and an alternative to the expensive and largely proprietary schemes that currently meet their performance requirements. Also, because it concentrates on the system-on-chip, chip-to-chip, and board-to-board connectivity issues involved in high-performance I/O, the RapidIO architecture does not conflict with any box-to-box networking protocols that may be preferred by customers of the networking OEMs. Furthermore, the versatility and scalability of RapidIO technology allows its use in a wide range of products.

"The RapidIO open standard is targeted at solving the 'inside-the-box' needs of future, scalable, low-latency networking and communications equipment," commented Rick Lacerte, an engineering manager/architect for Nortel Networks. "The software-transparent nature of the RapidIO architecture will allow rapid deployment, while the scalability enables distribution across a broad spectrum of Nortel Networks equipment."

Buses Run out of Gas

Like other advanced I/O schemes, RapidIO abandons simple and hierarchical buses and opts instead for a switched fabric of point-to-point connections. The switching devices employ a low-latency packet-switching scheme to handle multiple data streams simultaneously, increasing data flow rates to multiples of the bus transfer speed.

View an example here.

The reason for moving to a switched architecture is simple. Shared multi-drop buses have already been exploited to their full potential. Such techniques as increasing clock frequencies, widening the interface, pipelining transactions, splitting transactions, and allowing out-of-order execution have become increasingly expensive and are showing diminishing returns. So the RapidIO architecture employs a point-to-point, moderately parallel, packet-based interconnect. Other I/O schemes using a switched-fabric include Mercury computer's RACEway (from which RapidIO was partially derived), and the proposed InfiniBand architecture (that primarily targets LAN, SAN and WAN connections at the server level). Packet switching has also found increasing use for advanced I/O, for example, in SKY Computers' SKYchannel.

RapidIO is specified as a three-layer architectural hierarchy. The top level defines the overall protocol and packet formats to allow end points to process transactions. A transport specification provides the necessary route information for a packet to move from end point to end point. Finally, a physical specification contains the device-level interface such as packet transport mechanisms, flow control, electrical characteristics, and low-level error management.

Figure 2: The physical interface is where RapidIO shines. As part of its performance-boosting strategy, RapidIO uses LVDS (low-voltage differential signaling) for the electrical interface, primarily for backplane applications (linking pairs of connectors). LVDS is a proven technology that already enhances the performance of other I/O schemes (such as the Ultra SCSI bus) and has been standardized as IEEE 1596.3. In addition to boosting data rates, LVDS (with a 200-450mV swing) can lower power consumption. It is, however, restricted to short transmission distances (30 inches of trace on a standard circuit board).

LVDS allows RapidIO to promise significant interconnect bandwidth. The initial version of RapidIO will use an 8-bit channel with a 250-MHz clock. Signals are source-synchronous, however, so that RapidIO will operate in a multiple-clock environment. Data sampling occurs on both edges of the clock signal so that the resulting data rate 2 GB/s. Future implementations will include both 8-bit and 16-bit versions, providing data that can scale to 4 GB/s for the 16-bit interfaces.

In addition to its performance and cost advantages, RapidIO has the advantage of relative simplicity compared to other high-performance I/O schemes. Rick O'Connor, VP of Tundra Semiconductor (Kanata, Ont.) explains, "RapidIO is just message passing in a memory-mapped environment with the same load-store programming model people are used to with standard buses." As a result, the RapidIO scheme can be used without altering operating system software, and it needs no special device drivers. The architecture is also transparent to application software. So far as software is concerned, RapidIO interconnects look like a traditional microprocessor and peripheral bus. That simplicity and compatibility with older architectures should speed time-to-market.

How RapidIO Competes

One of the strengths that may allow RapidIO to survive and flourish is that it really doesn't have any head-to-head technological competitors other than the bulkier and higher-priced board-level architectures from which it was derived. To the extent that its role overlaps that of PCI-X or InfiniBand, RapidIO can outperform them. Also, if somebody wants to use RapidIO to upgrade, say, a CompactPCI system, it will happily coexist with the legacy boards and buses. In fact, early products using the RapidIO architecture will be used in conjunction with other buses such as PCI and PCI-X. Products based entirely on native RapidIO interfaces will emerge only when the technology's better performance and lower latency justify the extension from PCI-X.

Motorola has avoided the mistakes that Intel made with its proposed Next-Generation I/O architecture a few years ago. Intel had failed to line up support from its OEM customers who wanted a smooth transition from the PCI bus via the PCI-X enhancement, and did not want a new standard that was dictated by a dominant silicon supplier. Eventually, Intel was forced to merge the Next Generation I/O with the OEM-sponsored Future I/O to form the InfiniBand proposal. As a result, Intel wasted time competing with its own customers, and that allowed Motorola to seize the initiative with RapidIO.

One goal of the trade group will be to ensure that network equipment manufacturers, rather than silicon suppliers, keep control of the standard. Today's networking systems are needlessly expensive because of the bridge ASICs or FPGAs needed to link incompatible boards and chips. If RapidIO gains universal acceptance, all the boards will have the same interface and RapidIO interfaces will eventually be built into the microprocessor chips. Avoiding a north-bridge core logic chip will then reduce latency as well as cost.

Looks Like a Winner

By paying attention to economic, marketing and legal issues along with advances in technology, Motorola appears to have successfully grabbed the advanced I/O initiative from Intel and others. Although the window of opportunity is closing rapidly, there may still be time for some late entries in the crucial race between embedded I/O architectures. Texas Instruments, Myricom, Rambus and, of course, Intel are among the companies rumored to be preparing competing switched-fabric architectures for embedded applications. However, the open nature of the proposed RapidIO standard means that it is more likely to be modified than abandoned completely by the potential users. Its versatility and scalability suggest that it will survive in some form even if it doesn't grow to dominate the market.

Motorola and Mercury Computer both offer extensive technical data on RapidIO at their Web sites. Also, the non-profit trade association now focuses exclusively on the proposed standard. For the latest information on the architecture and its trade association, visit the RapidIO Trade Association's Web site at www.RapidIO.org.