Enabling Gigabit Ethernet for mainstream market adoption

Higher bandwidth networking technologies arrive in the marketplace on a regular basis. Stretching existing bandwidth capabilities well beyond existing requirements, industry pundits often laud these new technologies as the future direction for the mainstream networking market. In reality, the mainstream considers few new technologies, and even fewer achieve acceptance. This paper provides a high-level discussion of 10/100/1000Mbps Ethernet, its potential, and the enabling technology required for its rapid adoption by the mainstream market.

For a high-speed local area network (LAN) technology, "mainstream" refers to the volume-oriented market for servers and desktop computers. Successful mainstream adoption requires servers or network interface cards (NICs) with appropriate technical enablers. As the heart of any NIC or server connection, LAN controller chips provide these enablers and represent the functional keys for mainstream adoption.

Ethernet is the most widely deployed networking technology in the world today and industry analysts forecast its growth to continue well into the next decade. Over the two years, market interest in Ethernet technology provided at gigabit rates has grown dramatically. This is due in part to the success of Fast Ethernet, which taught users that the protocol was indeed scaleable to higher speeds in standards-based implementations. Consequently, users perceive the evolving 1000Mbps Ethernet standard as a natural extension to a familiar technology. The rapid development of the IEEE 802.3z standardization effort, targeted for completion in mid 1998, further assures users that 1000Mbps Ethernet will allow a tight link to existing networks.

For rapid mainstream adoption, the capability to provide 10/100/1000Mbps operation is an essential requirement for Ethernet LAN controller chips. Multi-speed operation allows implementers to deploy the technology strategically rather than tactically by offering an upgrade path for users. For example, most successful Fast Ethernet implementations operate at both 10 million bits per second (Mbps) and 100Mbps. The appeal of multi-speed operation extends to Gigabit Ethernet. Solutions offering 10Mbps, 100Mbps or 1000Mbps provide a stronger appeal than gigabit-only implementation and provide a stronger opportunity for success in the marketplace.

Mainstream adoption means use of the existing cable plant and Category-5 unshielded twisted pair (UTP) cable. While initial 1000Mbps Ethernet implementations will utilize fiber optic media, the IEEE 802.3ab working group is actively defining a standard for use of 1000Mbps Ethernet over Category-5 (UTP). This evolving standard defines the 1000Base-T implementation for Gigabit Ethernet and is targeted for completion in the early portion of 1999. 1000Base-T promises to provide a big boost in speeding the adoption of Gigabit Ethernet.

A key feature for LAN Controller chips is the incorporation of the Gigabit Medium Independent Interface (GMII). Part of the evolving IEEE 802.3z standard, the GMII defines the interface between LAN controller chips and physical-layer semiconductors, including the chips targeted for 1000Base-T. Consequently, LAN controllers lacking a GMII interface will face a difficult task of enabling operation over Category-5 UTP.

While 100Mbps and 1000Mbps data rates provide great promise for providing ample bandwidth for current and future applications, achieving a high percentage of this rate is critical for mainstream acceptance. The first step to realizing the performance capability is an advanced system interface.

The system interface is the bus structure through which the NIC delivers its information to the host computer. To enable mainstream acceptance, a LAN controller chip must provide an advanced system interface. Most networked desktop computers and servers use a standardized systems interface called the peripheral component interconnect (PCI) bus interface. Optimally, the LAN semiconductor should incorporate the PCI interface as part of the chip. This reduces the number of chips a NIC or server must use to provide LAN connectivity, thereby lowering the cost of the overall solution.

Secondly, the LAN controller's PCI interface must incorporate bus-master design that absolutely minimizes load on the host. This frees the host computer to perform other tasks. An important function of this interface is in minimizing host interrupts. Excessive use of interrupts increases the CPU load, and at high data rates, a poorly designed LAN controller can place a high burden on host computers. By contrast, highly efficient LAN controllers minimize the number of interrupts for each data transfer. In many cases, a high performance controller can eliminate the need for any interrupts when transmitting data, and minimize the use of interrupts for received data.

Finally, the LAN controller's PCI interface must maximize the amount of data transferred each time it accesses the host computer's PCI data bus. This functionality is one of the most critical elements to realizing the potential of a high-speed LAN implementation. In particular, an implementation that minimizes bus arbitration provides an essential enabler to realizing the potential of 10/100/1000Mbps Ethernet and translates to an attractive solution for the mainstream.

Dropped packets occur when incoming data arrives before the LAN controller has transferred an earlier packet out of its buffer memory. This most often happens when the host computer's PCI bus "holds off" the controller from transferring data received from the network. Dropped packets reduce overall network performance, as the lost data must be resent.

To avoid losing data, LAN controllers rely on first-in-first-out (FIFO) buffers to temporarily store inbound or outbound data. FIFO size must increase with the network speed to accommodate the increased amount of data that can arrive in a given time period. For 10/100/1000Mbps Ethernet, modern queuing theory suggests that controller buffers should approach nearly 1 Megabit. Solutions with smaller FIFO memory capabilities may compromise performance in high demand networking scenarios.

Another factor for 10/100/1000Mbps Ethernet is that the FIFO structure must be fast enough to accommodate data arriving at 1000Mbps. This dictates the requirement for the LAN controller chip to include an integrated FIFO rather than relying on external chips. An integrated FIFO ensures that the LAN controller will be more cost-effective provide a more tightly integrated solution than costly external high-speed FIFO chips.

TCP/IP (Transmission Control Protocol/Internet Protocol) is the pervasive communications protocol used in LANs and like any protocol, introduces overhead into the process of exchanging data. This overhead consumes MIPs (Millions of Instructions Per Second) on host computers.

One way to offload the host is to perform selected TCP/IP operations on the LAN controller chip. This capability conserves MIPs and increases overall performance. Advanced LAN controllers provide architectures to accommodate TCP/IP processing operations.

In addition to fast, efficient data transfer, advanced LAN controllers perform tasks that allow decision-making before data must cross the PCI bus. Functions that enable firewalls, virtual LANs, and limited routing capability can greatly enhance the solutions value for the mainstream market. By providing content-dependent functions, LAN controllers enhance their value to a larger mainstream market and offer policy-based management functionality.

A third element in offloading the host computer is optimized device drivers. A device driver provides the critical link between the host's operating system and its LAN controller. Important elements for optimized drivers are their synergy with the network controller chip, their overall size, and their ability to enhance rapid data transfer while minimizing the load on the host.

A final element in ensuring a speedy migration to 10/100/1000Mbps Ethernet is in managing costs. While multi-speed operation, a strong driver suite and solid performance are critical, the technology must be available at only a small premium relative to existing offerings. In today's market, 10/100Mbps LAN connectivity solutions can be found for less than $100. This level has resulted in rapid growth of 10/100 products, and will drive the use of more 100Mbps connections. For 10/100/1000Mbps network connections to become pervasive, the cost for end node solutions must drop from their current costs of $1500-$2000 for a fiber-based product to below $400, and copper-based solutions must become available for less than $200 by 1999.

These expectations are not unrealistic. By time the standard for Gigabit Ethernet is complete, vendors will be able to deploy fiber-based products at cost points similar to those for fast Ethernet in 1993. As the 1000Base-T standard matures and component vendors provide acceptable solutions, a Category-5 UTP offering will be available at prices to allow a rapid adoption. It is important to note that while consumers will purchase 10/100/1000Mbps solutions in large volumes, the majority of the solutions will operate at 10 or 100Mbps with the strategic capacity to move to 1000Mbps operation at later dates. Finally, ICs such as Jato's Network Accelerator Chips, are a new class of semiconductors that enable LAN equipment OEMs to deliver increasingly optimized enterprise network solutions.