Reverse Media Independent Interface (RevMII) Block Architecture

This article describes a design of a simple digital device able to connect two Ethernet MACs with configurable point-to-point link (Reverse MII Interface block). This link is proposed to be a simple and low-cost alternative to using Ethernet PHY in the system. The block might be used either inside an ASIC or on the system board (FPGA). The device described emulates two Ethernet PHY-level blocks connected together and is completely transparent to Ethernet MACs. RevMII is fully compatible with IEEE Std. 802.3u. Management interface (SMI) and Basic Register Set (Control and Status registers, defined in IEEE 802.3) along with MII test capabilities (such as Loopback, Power Down, and Isolate modes) are supported.

The link provided by RevMII is configurable via Serial Management Interface (SMI). The following standard features are supported:

• SMI support (refer to Clause 22.2.4, IEEE Std. 802.3, 2000 Ed.)
• Basic Register Set included:
• Control and Status registers (separate control register on each side)
• Loopback mode
• Isolate mode
• Speed/Duplex mode selection by each side
• Collision Test
• Power Down support.

Further additions and customizations, such as a SMI communication link between MACs using Extended Register Set are also possible. The main application for RevMII would be network routers and gateway ASICs. FPGA implementation is also possible due to low-speed and complexity requirements.

RevMII block is placed between two Ethernet MAC modules. Figure 1 shows the block diagram of the block and connection diagram that is used with RevMII. Data lines cannot be shared between Ethernet MACs on either side because MII does not support bus sharing from the MAC side—only one MAC may be the master at given time moment. The block diagram of RevMII (Figure 1) shows the following main components:

• Data multiplexers (Data Mux 0, 1)
• Management multiplexers (Mgmt Mux 0, 1)
• Management Entity containing Control and Status Registers (Mgmt) and Control Logic
• Collision/Carrier Sense Control Logic.

Figure 1:  RevMII block diagram

The MII Data Interface consists of three signals: TxD[3:0] (Data), TxEn (Data Enable), and TxEr (Data Error) for transmit direction and RxD[3:0], RxDv, and RxEr for receive direction respectively (those data interfaces will be referred to as TX and RX buses, these buses are 7 bits wide).

RevMII is controlled via the Serial Management Interface (SMI) as defined in IEEE Std. 802.3. Two Control Registers (for each side) and one Status Registers are implemented. In MII communication, Ethernet MAC always serves as a master and Ethernet PHY as a slave. RevMII is designed as two MII slaves connected to each other with shared control logic. Each side has a Data Mux, a Management Mux, and a Control Register. Status Register is shared by both management interfaces. Both Control Registers control Data multiplexers on each side, therefore both MACs have the same rights for controlling the link between them. Control Registers are independent from each other and they both affect bits in Status Register.

Collision/Carrier Sense Control Logic generates COL and CRS signals (which are used by MAC to observe a link status) as defined in IEEE Std. 802.3, Clause 22.1.

Clocks and Resets
MII data clocks (TxClk and RxClk) are not used in RevMII block (unless TX and RX buses are to be registered on block boundaries because of timing considerations). Management Clocks (MDC) are the real clocks in design, they clock Control and Status registers. Management Clocks are generated by Ethernet MACs and could be completely independent from each other. Separate reset signals (to be synchronized with management clocks) on each side are required.

1. Power Down Mode
   Activated by setting Power Down bit in any Control Register. Link is down and Data multiplexers are switched to port 2 (Figure 1, MACs read all zeros).
   
   
2. Isolate Mode
   Activated by setting Isolate bit in any Control Register. Link is down and Data multiplexers are switched to port 2 (exactly as in Power Down Mode).
   
   
3. Loopback Mode
   Activated by setting Loopback bit in any Control Register. Link is down and Data multiplexers are switched to port 1 (Figure 1), MAC receives the same data it transmits. This mode is used for testing purposes.
   
   
4. Collision Test
   If CollTest bit is activated in any Control Register, COL signal on that side will become high. This mode is also used for test purposes. Link Down bit in Status Register will show to the other side that transmission is impossible.
   
   
5. Data Transfer Mode
   If none of those modes is activated, Data Transfer can occur. Data muxes are switched to port 0 (so TX bus from MAC 0 goes to RX inputs of MAC 1 and vice versa). This is a default mode of operation.

Modes 1 through 4 will be referred to as Test Modes. If any side is switched to any of the test modes, LinkDown signal becomes active and shuts down the link. Also, CRS signals on both sides will become logic '1' (indicating that link is down), so the other side cannot transmit (see below).

Collision/Carrier Sense Logic
Figure 2 shows how the Collision (COL) and Carrier Sense (CRS) signals are generated. Collision Test signals are Collision Test bits in corresponding Control Registers. Collisions cannot occur in peer-to-peer connection (provided that both MACs support full-duplex mode), so in Data Transfer mode Collision signals are active only when the corresponding Collision Test bit in Control Register is set for testing purposes.

Figure 2:  Collision/Carrier Sense logic block diagram

In Data Transfer mode, the data multiplexers are switched to port 0 (Figure 1) meaning active link. In this case, if the link is idle (Data Enable signals on both sides are inactive) Carrier Sense signals are '0'. If data transmission is going on from any side, Carrier Sense signal on that side will indicate that by switching to logic '1'. In any test mode, both Carrier Sense signals become logic '1', indicating that link is not available (Clause 22.2.2). Collision and Carrier Sense signals are not required to transition synchronously to any clock, therefore simple combinatorial logic is used for their generation.

RevMII block may share SMI connection with other devices such as Ethernet PHY or other RevMII blocks and PHY address is used to distinguish SMI transactions directed to different devices. 5-bit PHY address used by RevMII is set up either at chip top level or at external pins (Clause 22.2.4).

The following are details on using the registers.

Control and Status Registers described above are part of the Basic Register Set. Additional control or status registers can also be implemented as part of the Extended Register Set. The only requirements imposed by the standard on additional registers are the following. The length of any register should not exceed 16 bits and they should be accessible by standard SMI protocol. The Extended Register Set can be used to control extra features such as speed/size of packets requested by one side from another or as additional asynchronous channel of communication between Ethernet MACs. This channel may work as follows. One of the MACs writes data to be transmitted to the other MAC to Extended Set Register(s) and the data are being transferred to Status Register accessible from the other side inside RevMII module. The other MAC will read the data when it initiates next SMI transfer. It should be noted that one MAC cannot force the other to read the data (in other words, send an interrupt) therefore only simple communication such as semaphores can be accomplished via the SMI interface.