A Novel Extra Low IF Receiver for the GSM Band

	ABOUT THE AUTHORS Evi Karayanni is a post graduate student in the Department of informatics, Athens University. Currently she is focusing on the transceiver design and simulation of various architectures concerning the third generation of mobile terminals. More...

Today, the mainstream of wireless-communications development targets third-generation mobile terminals and software-defined radios. This evolution demands a totally new approach to receiver and transmitter planning. Receiver architectures, such as direct-conversion receivers, seem to fulfill most of demands and to be most promising for the new epoch of personal communications. Nevertheless, the advantages of direct-conversion receivers, such as reduced power consumption, and even the flexibility between analog and digital domains, are offset by strong drawbacks, such as dc-offset generation, I/Q mismatch, excessive flicker noise in the baseband, and local oscillator (LO) leakage.

The extra low intermediate frequency (IF) receiver presented in this paper demonstrates most of the aforementioned advantages and is also free from the drawbacks of LO self-mixing products and even-order distortion.

This article analyzes receiver architecture for the most common TDMA (Time Division Multiple Access) standard. The paper's main objective is to determine the performance required for the different receiver building blocks, keeping in mind system quality measures such as C/I, C/(I+N), and SNR. We optimize the building block parameters to ensure realistic designs. The receiver performance is evaluated and compared to the most demanding GSM specifications.

The architecture under study is the extra low IF receiver. Figure 1 shows a block diagram of the receiver.

Figure 1:  Low IF receiver block diagram

The receiver uses an RF front-end stage, after which the signal is down-converted through an image-rejection circuit to the extra low IF of 455 kHz. The basic overall block diagram of the complete Rx chain consists of a bandpass filter at the front end of the receiver, which selects the band of interest. Then, a low-noise amplifier amplifies the signal, and the spectrum is down-converted to a lower frequency using a Hartley image-rejection mixer. The idea in image-rejection architectures is to process the signal and the image differently, allowing the cancellation of the image by its negated replica. At the very end, the power level of the signal is adjusted within the dynamic range of an 11-bit ADC. A variable gain amplifier performs this adjustment by compressing or amplifying the IF signal.

Image rejection is achieved partially by the front-end selectivity (duplexer and LNA selectivity) and partially by the incorporation of a Hartley image-rejection mixer. This device mixes the RF signal with the local oscillator input in quadrature form, then filters and shifts the results by ±45° before adding them together. The result is a rejection of the image by the following image rejection ratio:

q: Phase mismatch in deg.
Dg: Gain mismatch in dB
G: Gain in dB.

The performance of this topology is sensitive to phase and gain mismatches induced by the imperfections of RC//CR phase shifters, or by layout imbalances on the two mixing branches. Typically, you can get an image rejection ration (IRR) in the range of 30-40 dB with a gain mismatch of 0.2-0.6 dB and phase mismatch between 1° and 5°.

The main advantage of the extra low IF receiver, the very low IF, makes the IF filtering an easy-to-implement on-chip analog task. The low IF also reduces the power consumption of the analog-to-digital conversion, since the sampling frequency is in the range of a few MHz.

The main inconvenience of this architecture is the conventional Hartley-topology image-rejection receiver. This topology may not provide the required 66 dB of image suppression. New techniques are available, such as double-quadrature image-rejection receivers, which are less sensitive to phase imbalances and gain mismatches. Finally, due to the frequency similarity of the RF and the VCO signal, LO pulling is a potential problem, but can be compensated by buffering the quadrature outputs of the oscillator.

Figure 2:   Blocking profile for GSM

We subjected the receiver to tests including out-of-band and in-band (adjacent channel) interfering signals (Figure 2), inter-modulation tests, and image rejection tests. These tests include C/I measurements in the presence of a -99 dBm (worst case) GMSK signal and one sinusoidal blocker located from few kHz up to several MHz away from the signal. With the in-band interference, we consider the useful signal to be at the power level of -82 dBm and the various adjacent channels located from ±200 up to ±600 kHz. The resulting performance of the receiver under test is summarized in Table 1. and the building block specifications are shown in Table 2.

Table 1:  Summary of measured results of the receiver

The adjacent channel rejection is a measure of the capability of the receiver to receive a wanted modulated signal without exceeding a given degradation due to the existence of neighboring unwanted modulated signals. Figure 3 shows the ability of the receiver to reject an adjacent interference of -41 dBm located at 400 kHz offset from the -82 dBm GMSK useful signal, preserving the C/I and SNR criteria.

Figure 4 shows the performance of the receiver under a strong non-modulated band blocker of -33 dBm located at a 1.6 MHz offset from the –99 dBm GMSK useful signal.

You must take several tradeoffs into account to determine the performance of each building block of the receiver. One of these concerns is the gain of both the LNA and mixer structures. The LNA linearity is selected to keep gain compression low, in the presence of either strong out-of-band interfering or strong useful GMSK modulated signals. The gain of the LNA is fixed to account for the NF and the linearity of the following stages.

Mixer selection is critical for the topology under study. The selection between active or passive mixers is based on the device’s linearity, gain contribution, and noise figure. In this receiver structure, due to the existence of a single down-conversion stage, the gain distribution is a major concern. Although the linearity requirements are also severe, the selection of active mixers is very important.

Another concern has to do with the interference introduced by the strong modulated RF signals to the frequency of the local oscillator. These signals may corrupt or even degrade the signal of the voltage-controlled oscillator, changing it to a different oscillation frequency. This phenomenon exists partially due to the imperfect isolation between the mixer ports. In order to overcome the problem, we should buffer the outputs of the LO, before driving the mixer.

Table 2:  Optimized building block specifications

The phase noise of the LO interferes with the in-band blocking profile of the wireless standards. You choose this parameter so that the blockers mixed to the IF are always sufficiently attenuated to ensure proper performance. Accordingly, the phase-noise performance of the voltage-controlled oscillator should be, in the best case, –118dBc/Hz at 200 kHz offset. Although such a specification is difficult to achieve with a standard CMOS process, it can be accomplished using advanced BiCMOS technology in a fully integrated LC VCO.

Finally, the frequency responses of the front-end band-select and IF filters are presented in Figures 5a and 5b respectively. These filters are commercially available, so their performance is not taken into account in the overall optimization process of the receiver.

Figure 5:  (a) Frequency response of the band select front-end filter (b) Channel select IF filter