Bluetooth RF System-on-Chip: Product Design Challenges and Tradeoffs

The Bluetooth wireless interface—introduced by the Bluetooth special interest group (Ericsson, Nokia, IBM, Toshiba, and Intel) in 1998—specifies the air (radio) interface as well as the link and application layer, in order to enable the highest possible interoperability between units from different equipment manufacturers. Bluetooth relies on so called "ad-hoc connectivity," in other words, there are no base stations, no infrastructure, and no specific centralized call control/management facilities. All units are equal peers and any unit can establish the call to any other unit in the range.

Ad-hoc (implicitly wireless) networking requires a complete integration of:

• RF processing, including:
• antenna subsystem
• modulation, up-conversion and power amplification, RF power control
• RX signal amplification, down-conversion, filtering, and demodulation
• Baseband processing
• coding (encryption, scrambling, FEC/channel coding)
• decoding (decryption, scrambling, FEC decoding/correction)
• Resource (bandwidth) allocation mechanisms
• Channel assignment
• Medium access control for multiple terminal networks
• Quality-of-service (QoS) management, in other words, traffic prioritization
• Interference management (suppression/avoidance)
• Unit and service discovery mechanisms
• Power management
• Security management
• Interface to host system / application / user

Even if cited as a "low-cost" solution, high implementation complexity is required at the circuit level, spanning from the tricky 2.4 GHz RF circuit design, over advanced DSP techniques in the radio-baseband part towards HW encryption engines, processors with DMA capabilities and complex protocol stacks implemented in software.

The "low-cost"—or "highly integrated"—implementation would need to reduce dramatically the bill of materials to a single chip plus crystal, few decoupling capacitors, and connector. However, this market-driven trend imposes several design challenges such as hardware/software co-design, careful HW/SW partitioning, and good isolation between noise-sensitive RX input stages or PLL circuits and noisy digital circuits, for example, processors and memory arrays.

Bluetooth devices are operated in the ISM band, and exposed to high interference levels from the other Bluetooth and non-Bluetooth devices; this requires good interference avoidance and high dynamic range. At the same time, in a "low-cost" (and low RF performance) technology such as CMOS, the coexistence of the digital hardware on the same chip and large process variations make the design process tedious and risky.

Some design issues are combined with the uncertainty in the RF modeling of bonding wires, IC packages, PCB traces, and external RF components, such as baluns and antennas, requiring a complex design and simulation tool chain. In the TX direction, the requirements are imposed on in- and out-of-band spurious emissions, phase noise performance, and frequency stability, which cannot always be met with the "first shot."

Once the signal is down-converted to the first IF, it can be filtered, amplified, sampled by an ADC, and subsequently digitally processed. Some designs rely here on analog IF filtering and much simpler analog FM-discriminator-based demodulator designs. After demodulation, there is a slicer, converting the FM-demodulated signal to a binary sequence. The challenging issue in the slicer is a very short preamble of four symbols, leaving only 4µs for:

• Power-up ramping in the transmitter
• Receiver path stabilization
• Carrier frequency acquisition (decision threshold estimation)
• Symbol timing acquisition.

Fortunately, the following access code provides some redundancy and additional support for symbol timing acquisition. The Bluetooth standard also requires the implementation of radio-signal-strength-indication (RSSI), enabling the receiver to estimate the received signal power, which can be used for closed-loop RF power control.

Once an RX packet is demodulated, and the access code in the header is recognized, you can apply an on-the-fly forward error correction scheme (1/3 or 2/3 FEC) on the payload or not, depending on the QoS and the available link quality. The FEC functionality itself is deliberately simple, either implemented as three-fold repetition of the same data bit and decoded by a majority-decision circuit (1/3) or using shortened Hamming code for the 2/3 alternative. The HW implementation of FEC coding/decoding circuitry is a relatively low complexity task.

In the TX direction, you must encrypt, code, and modulate the data "on-the-fly" to reduce the processing and buffering delay to a minimum. Different modulation schemes such as open-loop modulation, the IQ up-conversion, or direct sigma-delta modulation can be applied. The optimization space covers issues such frequency drift, power consumption, spurious emissions, and process variation compensation methods by calibration or auto-calibration procedures.

Figure 1:  An example of a complete Bluetooth System-on-Chip

The RF-CMOS process provides metal-metal capacitors as well as thick top metal to generate good quality inductors and capacitors. Good quality models for the transistor as well as passive devices are available, for up to several GHz within the real silicon. The substrate has much higher ohmic characteristics compared to standard CMOS, so crosstalk between different functions can be reduced. Triple well technology (NMOS transistors can be isolated from the substrate) enables full isolation of analog and RF blocks.

A single conversion receiver with low IF frequency, usually in the range between 2 and 10 MHz, allows a much more relaxed channel select filter (CSF), so much lower Q components can be used. The resulting filter can be realized on chip, which reduces the pin count of the package and eases the PCB design. For the rejection of the image signal, an image rejection mixer is used, which doubles the current used for the receive mixing function. For systems with no external IF filtering, this is always required.

Figure 2:  Low IF receiver

The implementation of the channel select filter (CSF) leads to several compromises. The selection of the IF frequency has a great impact on the CSF, particularly on the Q of the needed filter parts. A low IF frequency enhances the stability of the filter, but the demodulation structure gets more complex and needs more silicon area. In addition, the dynamic range of the receiver gets limited by the 1/f noise of the filter. If implementing a switch capacitor filter, a careful selection of the clock is necessary to avoid interference.

Figure 3:  Channel select filter and tuning

With the aim of low power consumption, the design of the transmitter has to be evaluated carefully. For CMOS technology, all RF functions are very power hungry because of the MOS transistors. So all possible signal processing should happen at low frequencies.

Direct close loop modulation uses a frac-N PLL, which is capable of selecting the 79 BT channels with 1MHz spacing. The minimum step size of the PLL is much smaller and can be used for steering the VCO with the modulated GFSK transmit data. This structure is very robust and doesn't need extra external VCO supply stabilization.

Figure 4:  Direct close loop modulation

Direct modulation shows the best performance for transmitting GFSK modulated signals. Because this structure doesn't use up mixers, it is a very good choice for minimum power consumption. Having closed loop data transmission leads to a robust solution, which can easily be ported to an application board.

Dialog Semiconductor selected a low IF receiver in its solution, where the CSF is on-chip. The CSF works with auto calibration, so no external trimming is necessary. The signal is digitally demodulated where a high dynamic range independent of the process variation is achieved.

Figure 5:  Dialog Semiconductor's Bluetooth radio solution

For the transmitter, direct closed loop transmission is used to guarantee robust data transmission and low power consumption. Having single base band, digital demodulation and no up mixer, the required area of the device can be minimized. The die picture shows the single chip solution where the front end, base band, µC, memory, power management, and standard interfaces are implemented. Since battery connection of up to 5.6V is allowed by the power management system, no external regulator is needed.

Figure 6:  Die photo of a single chip Bluetooth device

This article considered the design of a low cost wireless data transceiver focused primarily on Bluetooth applications—for other wireless systems, different selections may be needed to provide the optimum performance.