Building Multi-Carrier TD-SCDMA Transmit Architectures

To help in that quest, the Chinese wireless community has developed the time-division synchronous code division multiple access (TD-SCDMA) specification, which combines the capabilities of CDMA and TDMA systems. Time division duplexing (TDD) is used in TD-SCDMA to separate the uplink and downlink channels. The frame length (or the TDD interval) of TD-SCDMA is 5 ms and the whole frame is divided into downlink and uplink by the single switching point. ¹

Both the uplink and downlink periods are divided into time-slot and the total number of time-slot is 7. The ratio for uplink/downlink can be re-configured to provide symmetric/asymmetric data services. Within each time slot, CDMA is implemented with the maximum spreading factor of 16. In other words, up to 16 code channels can be within the same time-slot. Compared with GSM, the basic unit in the frame of TD-SCDMA is resource unit (RU), which is defined as frequency, time-slot, and code channel with spreading factor of 16.

Under the TD-SCDMA structure, a basic TDMA burst transmission mode within a periodically repeated time frame (equivalent to GSM) was selected, operating in TDD mode. TDD allows transmission to take place in downlink and uplink directions alternately on the same radio carrier by periodically switching the direction of transmission.² The benefit of this solution is that the switching point between downlink and uplink can be set to a symmetric relation in the case of symmetric services or to a range of asymmetric values for asymmetric services. In this way, TDD offers improved spectrum utilization and traffic capacity for both types of service.

But while TD-SCDMA provides some nice performance benefits, it also brings with it some systems challenges to multi-carrier base station transmitter architectures. These challenges are caused by performance demands required in the TD-SCDMA specifications as well as performance limitations of existing components. In this article, we'll address the critical functional blocks and technology challenges related to building a multi-carrier transmitter sub-system for TD-SCDMA base station.

Technical Challenges
Like any new air interface specification, the TD-SCDMA spec provides some distinct challenges to designers. In the IMT-2000 specification, the TD-SCDMA radio interface is defined as a low chip-rate option of UTRA and UTRA-TDD specifications. This interface employs a quadrature phase-shift keying (QPSK) modulation scheme and requires that pulse shape filtering be applied to each chip at the transmitter. The impulse response of the pulse shape filter h(t) must be a root-raised cosine with roll-off factor is α = 0.22.

In the TD-SCDMA transmit architecture, digital-to-analog converters (DACs) and multi-carrier power amplifiers (MCPAs) must preserve the spectrum of several digitally generated carriers without corruption or spurious signal generation in adjacent channels. Thus, a base station transmitter must generate a minimum of spectral re-growth both on the individual carriers and as a result of intermodulation between the carriers. A DAC that can generate higher frequencies enables a reduction in the number of upconversion stages from two to one. Unfortunately, DAC performance deteriorates at higher frequencies.⁴.

Multi-carrier transmission differs from single-carrier radios, which rely on analog filters to remove undesired signals that could corrupt adjacent channels. Instead, the multi-carrier architectures must inherently limit distortion over the entire transmission bandwidth. An RF power amplifier is a non-linear device. When it carries a signal that does not have a constant envelope, a group of carriers or the sum of several CDMA signals, the power amplifier generates intermodulation distortion (IMD). Since the IMD power falls into adjacent channels as interference, advanced wideband power amplifier linearization schemes have become a key technology in multi-carrier transceivers.

According to 3GPP standard a TD-SCDMA transmitter should be designed for coexistence of TD-SCDMA BTS with GSM and DCS-1800 BTS's (TSM 11.21). To lower the linearity requirements for the multi-carrier power amplifier, the adjacent channel leakage ratio (ACLR) specification for the DACs shall not exceed the values specified in Table 1.

Table 1: ACLR Frequency Offset and Minimum Requirement

The peak-to-average power ratio (PAPR) of the TD-SCDMA signal depends on the number of codes and carriers. The maximum PAPR occurs if all codes and carriers add in phase. System simulations have showed that the input signal of the DAC can be clipped up to 9 dB. Thus, the performance of the DAC should not be significantly decreased by the transmit signal processor.

Component Performance Requirements
Figure 1 shows a multi-carrier TD-SCDMA sub-system that incorporates all of the elements traditionally found in a base station transmitter, with the addition of a linearization element in order to meet multi-carrier adjacent channel power specifications.

Let's look at the main specifications required for the key transmitter components. We'll start with the transmit signal processor (TSP).

The TD-SCDMA multi-carrier transmitter requires a 104-MSample/s TSP. This processor is located between digital signal processors (DSPs) and high-speed DACs in a base station transmitter. The 16-bit DAC allows many TSP summed processed channels to be transmitted over several MHz of bandwidth where the peak-to-average output signal ratio is high, with average output signal level at a fraction of the full-scale range.

The TSP is equipped with a programmable coefficient finite impulse response (FIR) filter stage that allows pulse shaping and anti-imaging filtering. A programmable power ramp up/down unit is also housed on board the TSP for power ramping on a time-slot basis as specified under the TD-SCDMA specification.

In the TSP, a fifth-order cascaded integrator comb (CIC) filter stage and a highly flexible re-sampler incorporated into a second-order CIC filter enable both narrowband and wideband carriers to be processed in a high-speed sample stream. A higher-resolution numerically controlled oscillator (NCO) is also included for flexible frequency planning. The high-speed NCO can be used to tune a quadrature sampled signal to an IF channel. The NCO can also be directly frequency modulated at an IF channel.

Multi-carrier phase synchronization pins and phase offset registers on the TSP allow intelligent management of the relative phase of independent RF channels. This intelligent management capability supports the requirements for phased array antenna architectures, which are used in TD-SCDMA. Additionally, intelligent phase management allows the TSP to deal with wideband peak/power ratio to minimize clipping at the DAC.

DAC Requirements
In addition to the TSP, the multi-carrier TD-SCDMA transmitter architecture required a state-of-the-art 16-bit DAC. This DAC is important because it enabled the system to convert interpolated transmitter data in baseband or IF waveform reconstruction applications requiring high dynamic range. The 2X/4X/8X selectable interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the DAC passband noise/distortion performance. These on-chip filters enable wideband multicarrier architectures to suppress in-band noise and distortion while simplifying the reconstruction analog filter that follows the DAC. The independent channel gain and offset adjust registers allow the user to calibrate local-oscillator (LO) feed-through and sideband suppression errors associated with analog quadrature modulators. A 6-dB gain adjustment range can also be used to control the output power level of each DAC.

Interpolating DACs feature the ability to perform Fs/4 and Fs/8 digital modulation and image rejection when combined with an analog quadrature modulator. In this mode, a DAC accepts I and Q complex data (representing a single or multi-carrier waveform), generate a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and present these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process.

An internal phase-locked loop (PLL) clock multiplier is also included in the DAC to generate the necessary on-chip high frequency clocks. The clock multiplier can also be disabled to allow the use of a higher performance external clock source.

Handling Upconversion
In the TD-SCDMA transmit architecture, a silicon RF I/Q modulator performs signal upconversion from IF to RF (RF range 0.8 to 2.5 GHz). This modulator provides excellent phase accuracy and amplitude balance to enable the direct modulation of signals to RF.

To ensure high accuracy and amplitude balance, a differential local oscillator (LO) input is applied to a polyphase network phase splitter that provides accurate phase quadrature from 0.8 to 2.5 GHz. Buffer amplifiers are inserted between two sections of the phase splitter to improve the signal-to-noise ratio (SNR). The I and Q outputs of the phase splitter drive the LO inputs of two Gilbert-cell mixers. Two differential voltage-to-current (V-to-I) converters connected to the baseband/IF inputs provide the baseband/IF modulation signals for the mixers. The outputs of the two mixers are summed together at an amplifier. The quadrature inputs are directly modulated by the LO signal to produce the RF output.

Making a Three-Carrier Architecture Work
Above we discussed the performance capabilities required by each component in the transmit architecture. Now let's look at how these components work in a three-carrier TD-SCDMA transmit architecture

Figure 2 shows a three-carrier TD-SCDMA TSP configuration where IF upconversion is done in a digital manner. In this configuration, the DAC that follows the TSP is updated in a rate of 368.64 MSamples/s (1.28 MChips/s 36 8). The objective of TSP filtering is to constrain the bandwidth of the output signal so that it remains below the transmit mask defined in the TD-SCDMA specs.

In the architecture highlighted in Figure 2, the baseband signal has a chip rate of 1.28 MChips/s. The digital upconverter in this architecture runs at a 92.16 MHz clock rate and performs the root-raised cosine filtering, interpolation, and frequency shifting. Up to three TD-SCDMA carriers can be placed anywhere within a band of 20 MHz. The serial data source drives data at f_SCLK = f_CLK/2 = 40.96 Mbps (or 1.28 32 = 40.96 Mbps) per TSP processing channel. The master clock runs at 92.16 MHz, which allows the programmable FIR filter to calculate 36 taps.

In the three-carrier transmit architecture, the programmable coefficient FIR filter interpolates the input signal by a factor of 3 and pre-compensates for the CIC filter roll-off in the passband. The FIR filter output rate is 3.84 MSamples/s per processing channel.

The second filter stage, a fifth-order CIC (CIC5) filter provides an interpolation of L_CIC5 = 6. The CIC5 output rate is 23.04 MSamples/s.

The third filter stage, a second-order re-sampling CIC, provides interpolation of (L_rCIC2 = 2). The CIC2 output rate is 46.08 MSamples/s (complex samples).

In the three-carrier TD-SCDMA transmit architecture described here, the CIC and NCO save power by running at the complex rate of 46.08 MHz. The interpolated TD-SCDMA signal is frequency translated to an IF = -5.76 MHz by a sine/cosine sequence generated by the NCO and the carriers are shifted by the TSP to a frequency band of -15.76 MHz to 4.24 MHz.

The error vector magnitude (EVM) is calculated by observing the time-domain impulse response of the actual TSP filter matched by an ideal root raised cosine receive filter. Since an ideal root-raised cosine filter has an infinite response, a large number of symbols is used to insure that no significant error vectors are aliased by the Fast Fourier Transform (FFT), which would result in an inaccurate measurement. This is verified by noticing the extremely small results in the center of the impulse response plot. In our example, the EVM is 0.93 %.

Linking in the DAC
A DAC is configured to accept interleaved I and Q data from a TSP (as shown in Figure 1 above). The data interface is 32 bits wide, 16 bits for the real and 16 bits for the imaginary part. The dual DAC generates a complex modulated IF signal, which is then translated to RF by an analog quadrature modulator. The image rejection and frequency shift capability of the DAC determines the requirements of the following analog filter stages.

The DAC interpolates the data by L_DAC = 8, thus resulting in a sample rate to 368.64 MSample/s. This configuration allows the 43-tap first stage filter to run at 368.64/8 = 46.08 MHz. The 8X interpolation allows the DAC to run near its maximum rate which increases separation, reduces sin(x)/x roll-off, and reduces DAC distortions associated with large steps between samples. The complex F_DAC/8 mixer stage shifts the band by 46.08 MHz. The TD-SCDMA carriers are placed to a band from 30.32 to 50.32 MHz. The band is centred to an IF of 40.32 MHz. Figure 3 shows a blue rectangle within it three filtered TD-SCDMA carriers at DAC output can be located.

In a quadrature modulator that follows a dual DAC two mixers are operated in quadrature (sine and cosine LO's are mixed with DAC complex signal output). The two mixer outputs are summed internally to perform mathematical operations according to the phase relationships and signs of the frequency components. In this manner, the quadrature modulator augments one sideband and diminishes the other while suppressing the LO.

In this configuration the quadrature modulator modulates the DAC output to a frequency band of 2110 to 2170 MHz. The input of the device accepts a 1-V peak-to-peak differential input signal centered on a common-mode voltage ranging from 0.25 to 0.50 V while the output supports a differential-ended interface to a SAW filter. This device maintains less than 1% quadrature phase imbalance such that -36 dB sideband suppression can be achieved (with gain calibrated to less than 1%).

Wrap Up
Clearly, as this paper pointed out, the emerging TD-SCDMA provides some stringent demands on base stations transmitter architectures. In this article, we article described the analog, digital, and mixed-signal components required to build an image-rejection base station transmitter architecture. Designers can use this information as a guide during the design/development process.

References

1. CWTS, "General Description of TD-SCDMA, July 2001.
2. K. Kammerlander, " Benefits and Implementation of TD-SCDMA", Proceedings of International Conference on Communication Technology , WCC - ICCT 2000, Volume: 2 , pp. 1013-1016.
3. CWTS, "Physical channels and transport channels onto physical channels" TS C102 V3.0.0 October 1999.
4. A. Bidra, "High-speed wideband DACs permit multi-carrier cellular basestations", Electronic Design, December 18, 2000, pp. 64-70.

About the Author
Dimitrios Efstathiou is a systems engineer with Analog Devices. In this role, Dimitrios is involved in the design of algorithms and architectures for wireless base station transceivers. He can be reached at dimitrios.efstathiou@analog.com.