Milestone: Samsung 73-nm flash

The torch has been passed: Samsung's July launch of a flash memory at the 73-nanometer technology node marked the first time that DRAM had been beaten to production at the leading-edge lithography feature size. Today, available DRAM technology is sitting at 90 nm. Samsung's competition for ramping up the latest process technology seems to be internal, between its own flash and DRAM groups. Not surprisingly, then, the introduction of a 4-Gbyte NAND flash at 73 nm is a full year ahead of the Semiconductor Industry Association road map estimate of 2006 for the first year of introduction for the 70-nm node.

It's worth briefly tracing the history of the flash process developments that have led to the point where flash has attained the minimum feature size of any device on the market. Then we can put Samsung's latest flash technology into perspective for the future, with possible floating-gate replacement technologies.This report will outline the most important features of the Samsung 73-nm flash technology revealed by Semiconductor Insights' analysis of the structure and process in relation to both history and forecasts. Samsung's new flash device will be compared with the No. 2 NAND, from Toshiba. That analysis boils down to a comparison of single-level cell (SLC) with multilevel cell (MLC) technology.

Flash's road
Tracing NAND flash back to the early days at Samsung and Toshiba in 1989 provides much less information on trends than does a review of DRAM, which elevated Gordon Moore's observations into a law. Nonetheless, meaningful trends for NAND flash extend back about 18 years. Price per megabyte is on the same trend line as DRAM but lagging by nearly three years. Die cost is inseparably linked to die size and to the printed feature size, so we have a very good picture of the position occupied by flash technology until recently. Flash has definitely closed the gap.

Lithography sets a boundary for density, but flash manufacturers eventually bypassed the most important lithographical limit: the floating-gate space. Historically, the floating-gate space defined the benchmark of the technology used in a particular device. But then process engineers began growing sidewall spacers onto floating-gate masks to shrink the floating-gate space dimension to well below the limits of the lithography tools of the time.

Shrinking minimum printed features and critical dimensions is only part of the story. A floating-gate flash cell still requires a separate mask to define the floating gate. Alignment of those masks presents a further constraint to creating a functioning device of given cell size.

Toshiba engineers were the first to introduce a fully self-aligned cell at 90 nm with the 4-Gbyte multilevel-cell device earlier this year. The complete self-alignment of features-from the shallow trench isolation defining the transistor channels through formation of the floating-gate up to the control-gate polysilicon-is an elegant technique that avoids the potential yield problems of mask misalignment. This fully self-aligned cell is a key enabler for further scaling of floating-gate technology.

Floating-gate alternatives
Sonos (silicon-oxide-nitride-oxide-silicon) devices like those from Spansion and Infineon have emerged as viable alternatives to floating-gate designs. Semiconductors mimic the fashion world here by making everything old new again. After all, the original EPROMs were all MNOS (metal nitride oxide semiconductor) types; that is, they depended on charge trapping in a dielectric to program a cell, much as Spansion's MirrorBit technology and Infineon's Sonos devices do today.

The major advantage of these approaches is the physical separation of charge in a multibit cell. The devices have found strong markets by storing more bits per square millimeter than the volume possible with floating-gate devices manufactured using equivalent lithography tools. The structures still have a long way to go, however, to displace floating-gate designs. More important, they suffer scaling problems of their own and may even stop scaling effectively before floating gate does.

The most-talked-about solution to the end of planar CMOS device scaling is the FinFET. Infineon claims to have achieved the world's smallest FinFET-based flash cell, produced with a 50-nm feature size. The design allows a central silicon "fin" channel to be gated from either side. Charge is stored by trapping, as in Infineon's current Sonos memories.

Samsung recently announced its own "3-D" approach to scaling flash to 50 nm.

See photo: Samsung's 4-Gbyte part contains the smallest features of any memory product analyzed.

Describing use of the third dimension for a flash cell as an innovation has always seemed odd; after all, control gate coupling to the floating gate has always relied on the third dimension. However, Samsung is talking about its 3-D transistor structure, which is most likely similar to the recessed-channel-access transistor (RCAT) seen recently in its 90-nm DRAM. Samsung etches a trench into the silicon to stretch the channel length down into the third dimension. The company correctly points out that this will provide added margin to crosstalk between floating gates. The innovation is one more reason to believe that Samsung will have some type of floating-gate technology going strong well past 45 nm.

For content storage, Matrix Semiconductor is stacking bits vertically as well as building a 90-nm memory technology on old 150-nm logic lines. Since access transistors and control circuitry reside underneath the memory bits, older lithography does not increase the die area and cost. Innovative use of 150-nm lithography and more-advanced mask making allow memory half-pitch at nearly 50 percent less than the logic design rules. This design is certainly nonvolatile but does not enable rewriting of the memory. It is a very attractive alternative to flash for one-time storage of media files such as electronic film. The inability to reuse the storage for new files is offset by the instant creation of a permanent archive of the digital image files. For instance, Matrix is sampling a 128-Mbyte multimedia card solution and plans to manufacture gigabit devices in the near future.

Samsung self-aligned cell
Samsung may not be the first to enter the market with a fully self-aligned cell, but the company has a long history of taking any technology to its limit. The 73-nm flash is Samsung's first use of the self-aligned technology but is by no means the limit. Look for Samsung to leverage the technology down to at least 32 nm.

The current, 4-Gbyte Samsung device contains the smallest features of any memory device we've analyzed. But Samsung relaxed several critical dimensions compared with what it announced at the International Electron Devices Meeting in 2003. Here are the main features:

• 73-nm word-line (control gate) half-pitch;
• 54-nm space between floating gates (not 40 nm, as published);
• 90-nm control gate (not 70 nm, as published;
• larger bit line contacts (90 nm achieved, vs. 70 nm published); and
• tungsten silicide over polysilicon (not tungsten over polysilicon).

Samsung has obviously overcome several problems that many analysts point out when forecasting the end of floating-ate flash. Key among those is the crosstalk between floating gates. This did not appear to slow the introduction of the 73-nm device. The 54-nm space between floating gates compares with 90 nm just two years ago.

It is easy to focus on the memory cell when considering the technology scaling, its limits and the innovations used to overcome these. However, one should not overlook the role the control logic plays in creating a stable, high-yield device. Samsung introduced a new structure for the peripheral transistors in the 73-nm flash. Since floating-gate flash technology always requires two levels of poly separated by a robust dielectric, some interconnection scheme is always required.

Devices manufactured before this year typically used a mask to etch a portion of the second polysilicon and the underlying dielectric so that a split contact of tungsten could make contact to both levels. Samsung used a more-obvious approach: It simply removed the dielectric before depositing the second polysilicon level. The move averted yet another potential misalignment problem, with the split contact.

MLC vs. SLC
Although 73 nm represents the pinnacle of lithographic-patterning achievement, the main driver for flash is cost per bit. That means bit density on the silicon rules. Samsung's approach is to leverage its advanced-manufacturing expertise to pack the most bits onto a flash die.

It is also possible to store more than one bit at each cell location, however. That was Toshiba's approach with its 4-Gbyte MLC device, which stores 2 bits at each physical cell location by splitting the amount each cell is programmed into four levels.

The Toshiba 4-Gbyte MLC flash uses 90-nm process technology but still manages to pack the same amount of storage onto a die that is about 12 percent smaller than Samsung's. The flash team at Toshiba has done an excellent job of maintaining array efficiency on the die despite needing to program read, reference and error correct for twice as many voltage thresholds in the cell. In fact, array efficiency on the Toshiba device is identical to Samsung's: 62 percent.

The MLC technology does pay a price, however, in speed. Access and programming times are two to three times slower than for the single-level design from Samsung.

Indeed, the SLC marketing program is taken very seriously at Samsung. Its Web site goes into great detail not only on the speed advantage of SLC but also on the potential endurance, data integrity, voltage and power concerns associated with MLC design.

I cannot comment on the impact of the MLC design on any benchmark beyond physical analysis of the Toshiba device. Nonetheless, Toshiba designers did a great deal to close the programming speed gap on SLC technology.

Internal programming measurements of the 90-nm 4-Gbyte design proved that Toshiba reduced program time by a third over the 130-nm generation. For many consumer applications, however this speed difference will be virtually undetectable, and density will sell the product.

Don Scansen (dons@semiconductor.com), process technology manager at Semiconductor Insights Inc. (Kanata, Ontario)