Cracking the Analog-Design Nut

Since a large percentage of system-on-a-chip (SoC) designs include some analog circuitry, designers are faced with the problem of integrating analog design into the predominantly digital SoC design flow. This has been difficult to do because:

1. While digital design incorporates a top-down design flow, designing analog circuits is basically a bottom-up operation.
2. An analog block on a chip generally has more dimensions in its design space (in other words, has more design variables and constraints) than does a digital block, adding to the block's design complexity.
3. For chip development, there are far fewer good analog designers than there are digital designers.
4. For design reuse, digital portions of a chip may use hard or soft silicon IP (SIP). Designers only have hard SIP available for analog portions of a chip that comprise more than basic functions. Process-specific hard IP provides known performance, but cannot be modified for slightly different functions or other processes.
5. Analog/mixed-signal chip-design tools are less mature than their digital counterparts.

The design-tool problem is of particular interest since one tool, logic synthesis, demonstrates the large gap between chip-based digital and analog design capabilities. Logic synthesis, which commercially debuted in the 1980s, introduced a completely new paradigm for digital-chip design. The ability to go from a chip's architectural description in RTL to a library-dependent gate-level description allowed digital-chip design to become top-down. Designers now had an automated mechanism (albeit one that requires good designer knowledge of the synthesis tool and the design) for going from an architectural to a structural representation of a digital chip and the blocks within that chip.

A complete synthesis tool for generating the analog portions of a chip is not in mainstream design. Analog synthesis is a much more difficult problem. Even if you have the correct circuit to use for a particular analog function, such as a PLL or an ADC, you still have to optimize many component parameters to meet that circuit's design constraints. These parameters include component values, such as resistance and capacitance, as well as transistor sizes and geometries.

The lack of adequate analog synthesis points out the need for a good analog-circuit optimization tool for SoC designers—the optimizing problem is really the limiting factor to higher analog/mixed-signal design productivity. Circuit configurations for many analog functions are well known; however, optimizing the function's circuitry for a particular application can take many weeks or even months, depending on circuit complexity and design constraints. Furthermore, once a designer has optimized a circuit's parameter values, the layout of that optimized circuit is another lengthy process.

To successfully integrate analog design into SoC chip design, we need a new breed of analog-design tools, focused on circuit optimization and physical implementation. There are a handful of EDA companies working on such tools, including Barcelona Design, ADA, Neolinear, and Antrim Design Systems.

Some of these companies offer analog/mixed-signal SIP, as do some SIP/library vendors such as NurLogic, specializing in communication-centric mixed-signal cores. Barcelona (Picasso, Dali, Miro, Goya), Antrim (MSS), Neolinear (NeoCircuit), and ADA (AMS Genius) all have products with some degree of analog/mixed-signal circuit synthesis. Barcelona (synthesis tools include floorplan placement now, with routing under development) and Neolinear (placement and routing with NeoCell) also have tools for automated analog layout, although the companies' products different in terms of degree of automation during layout and complexity of the circuits the tools handle.

Ideally, what SoC designers need for integrating analog functions on a mostly digital chip are design tools and SIP for:

1. Analog synthesis that will produce an optimized circuit based on that circuit's design specification. Since there are often many different analog architectures for a given function, such as an op amp or an ADC, the design tool must also help the designer choose the best architecture for a given set of specifications.
2. Analog/mixed-signal layout that considers complex details such as transistor geometry, device matching, and device orientation.
3. A broad range of analog SIP that includes behavior models, preferably in analog/mixed-signal versions of Verilog or VHDL, along with traditional Spice models. Soft SIP, for all but basic analog functions, is still a ways away. All hard SIP must be verified on the silicon process that the designer is targeting.
4. Analog/mixed-signal tools must be able to fit into an existing SoC design methodology.

While there are not yet commercial design tools available to completely accomplish all of these needs, the tools that are around have made progress in solving some of the analog-design problems. Look for EDA companies such as the ones mentioned in this article to come out with vastly improved tools for analog/mixed-signal chip designs within the next 12 to 18 months, if not sooner.