ADCs and Digital Wireless Base Stations

While the world is moving more and more into an all-digital domain, the fact remains that many natural phenomenons are analog in nature. Probably the foremost example of a basic analog signal is that of human speech. Converting analog speech into digital bits, and then compressing the resultant data stream so that it can be stored, processed, and/or transmitted has been the subject of numerous research projects and has led to the development of multiple compression/decompression schemes, but scant attention is usually paid to the analog-to-digital converter itself. However, in the case of digital wireless telephony, the A/D converter device itself (ADC) is a crucial component in being able to make the next systems level technology leap. In this technical overview, we look at some of the characteristics needed in an ADC intended for the next generation wireless system.

Material for this article was provided by both Analog Devices and Lucent Technologies. Both companies have looked at the particular demands of the wireless base station market and both have introduced A/D silicon optimized for that application.

Traditional base station designs use a separate receiver for each channel, each receiver tuned to a fixed channel that may range from 30 kHz to 3 MHz wide, depending on the wireless standard. The output of each tuner is fed to an ADC and then to a digital signal processor (DSP) for further processing. Because a base station often has 10 or more channels per cell, a wireless operator has to manage a cabinet of heat generating, power consuming, and expensive receiver electronics.

A newer approach to base station design uses a single, very high-performance wide-band radio receiver to capture and digitize the entire cellular band (30 MHz wide versus 30 kHz for a single channel in some standards) as a single block of data. The high bandwidth of the radio signal coming into the base station requires high sampling speed from the ADC, but the cost of a single radio stage is shared across all wireless channels. Because the whole block of signals is digitized at once, this approach is often known as block radio.

With block radio, all the processing is done in the digital domain. Channel selection to baseband is performed using digitally-controlled oscillators and digital multipliers. Once the channel selection is made, digital filters decimate the 20-70 MHz incoming signal to a slower rate that can be processed by a DSP chip.

By reducing the analog content of a base station's electronics, block radio improves on cost, reliability, and power dissipation. Digital components are less susceptible to drift, eliminate the need for trimming, and perhaps more important, are able to be upgraded with new software so that the base station can be reprogrammed to work with new standards. However, digitizing a wideband wireless waveform and extracting the signal from the background noise places some severe design constraints on the ADC device.

In block radio the Intermediate Frequency (IF) filter must be wide enough to allow the entire band to be converted. Consequently, the ADC must have high sampling speed. Unfortunately, the wide-band input is also likely to contain signals transmitted by other wireless users from other wireless providers, and may even contain a mix of AMPS, Global System for Mobile Communications (GSM), Time Division Multiple Access (TDMA), and Code Division Multiple Access (CDMA) transmissions. The base station receiving these foreign signals does not have the ability to reduce their transmission power, as it does with the signals under its system control. These foreign signals may cause significant in-band distortion products (called blockers) that can block the desired signal. Therefore, the ADC needs exceptional distortion performance, including low non-linearity and wide dynamic range.

Lucent Technologies
With this block architecture in mind, Lucent Technologies Microelectronics Group in 1998 introduced the CSP1152A, an ADC designed to address the performance requirements of block radio. The CSP1152A helps carry wireless base stations to the next level of performance by enabling many analog components to be replaced with digital electronics. The CSP1152A is a CMOS ADC that has the high speed needed to digitize high-bandwidth radio signals, the high dynamic range to help pull low-power signals from high-power noise environments, and on-chip dither to reduce distortion and extraneous signals up to 100 dB below maximum signal levels, thereby improving signal-to-noise performance without additional circuit cost. The CSP1152A chip is a member of Lucent's growing wireless-communications integrated circuit family and can be used for GSM, CDMA, and TDMA wireless standards.

Analog Devices
Analog Devices (ADI) was actually first to offer a product in this space. In mid-1994 the company introduced the AD9026, a TTL chip, and the AD9027, a functionally equivalent chip using ECL technology. At the time, the ADI products, with 12-bit accuracy and exceptional linearity at up to 31 Msps sampling rates and a spurious free dynamic range of 73 dB, were real breakthroughs for block radio applications. Both devices use a three-pass sub-ranging architecture and digital error correction to achieve 12-bit accuracy with relatively low power consumption.

At SFDR levels of 90 dB and above, circuit board implementation and the quality of passive components also become important design issues. Clock jitter is also a significant problem in radio frequency (RF) design. Another issue is that the high-speed signals at the output of the ADC can leak back into the input of the converter and degrade SFDR. To address this issue, Lucent's CSP1152A uses a low-voltage differential signal (LVDS), a low-noise, high-speed electrical interface that moves data from the converter chip to a DSP with improved reliability by reducing coupling of digital to analog signals. LVDS receivers are now commonly available as standard products or as ASIC libraries, making interface to the CSP1152A easy.

SNR
The signal-to-noise ratio in a wideband architecture benefits directly from a process called oversampling, which reduces the noise floor for a constant bandwidth signal. For example, consider a wireless signal with a 30 KHz bandwidth. With an ADC sampled at the Nyquist rate (60 kHz), the full noise power of the converter will be in-band. But if we raise the sampling rate to 120 kHz, then only half the noise power is in-band and the SNR is improved by 3dB. But in our block radio design, the sampling rate with the CSP1152A is 65 MHz. This is 1083 times the required sampling rate and it results in an improvement of 30dB, calculated from the equation SNR = 10log ((sampling frequency/2) * (1/ signal bandwidth)). This added SNR is called processing gain. This means that an ADC with a SNR of 65dB over the Nyquist band will have an SNR of 95dB after processing gain. Processing gain applies only to random noise; it does nothing to improve a converter's linearity performance and thus does not improve the harmonic distortion or SFDR.

Bandwidth
Another important specification for an ADC used in block radio is the sample and hold (S/H) bandwidth, typically specified as the input frequency range that causes the converter gain to be reduced by 1 to 3 dB. In block radio the input sampler is often used to perform a mixing function as well as a sampling function, thereby eliminating the need for additional external components. This approach allows for relaxation of the linearity requirements of some of the RF and IF analog blocks. The input signal to the ADC may have frequency components as high as 250 MHz, so the S/H bandwidth must be much higher.

The mixing property of an ADC's sample and hold circuit is called undersampling. In an undersampling operation, a frequency translation occurs. The frequency range of the input signal and the sampling frequency must be carefully chosen so the resultant signal at the output of the sampler is in the range of DC (0 Hz) to half the sampling rate of the converter.

The design of the ADC sampler can greatly limit its usability in undersampling. The sampler must not only have wide bandwidth, but also display high linearity in the frequency range of interest. These performance requirements are difficult to achieve when active electronics are part of the sampler, as is the case with bipolar technology. In contrast, to form a sampler with Lucent's CSP1152A, a simple CMOS switch and a capacitor are all that is required. This simple, high-performance circuit can be used because the sampler drives a CMOS operational amplifier (op amp), which places no DC load on the sampling capacitor and imposes no DC offset on the signal sample.

Reducing ADC Non-Linearities with Dither
Modern high-speed, high-resolution converters are made using multi-stage, pipelined converter techniques. A problem with this approach is that linearity errors caused by mismatches between the stages can significantly affect SFDR and linearity. One method to address this problem is to add dither to the input signal to de-correlate (randomize) the linearity errors of the converter. Correlated spurious tone energy that cannot be handled by downstream signal processors is converted to random noise that can be reduced by processing gain. This use of dither for linearity improvement is accomplished by making linearity errors more uniform across the converter's range and is different from the use of dither to decorrelate the quantization error present in any ADC.

Analog Devices has proposed introducing high-level, low-pass dither signals into the input of the ADC. Because communications signals are bandpass in nature, the low-pass dither will in theory not affect the in-band signal. In practice, however, in-band noise modulation effects can be seen and the SFDR of the converter is degraded in the presence of signals near the full-scale range of the ADC. According to some, another problem with this approach is that external components must be used to generate the broadband noise, filter it and then add it to the signal path.

Lucent's chip uses a dither signal generated on-chip. The dither signal itself does not appear at the output of the converter because digital post processing removes it. This dither method is made possible by the availability of switched capacitor circuits and high-density digital logic found only in a CMOS design. Dither improves the SFDR of the converter at all signal levels, and because the function is on-chip, the implementation cost is low.